AD6624

Obsolete

80 MSPS, Quad Receiver Signal Processor

Data Sheet (Rev. B)

Viewing:

Part Details

80 MSPS Wideband Input (14-Bit)
Four Independent Digital Receivers in a Single Package
Digital Re-sampling for non-Integer Decimation Rates

Programmable Decimating RAM
Coefficient FIR Filters
3.3 Volt CMOS
JTAG Boundary Scan, Built in Self Test
(BIST) Capability

Suggested Replacement Parts

Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)

Documentation

Data Sheet 1

AD6624: Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) Data Sheet (Rev.B) 05/05/2001

Application Note 1

AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev.0) 07/26/2006

Technical Articles 3

Smart Partitioning Eyes 3G Basestation 10/18/2002

Soft Radio Runs into Hard Standards 03/19/2001

Basics of Designing a Digital Radio Receiver (Radio 101) 03/06/1998

Product Highlight 1

Introducing Digital Up/Down Converters: VersaCOMM™ Reconfigurable Digital Converters 03/08/2008

This is the most up-to-date revision of the Data Sheet.

Tools & Simulations

AD6624 (AD6624A) IBIS Models 2

Latest Discussions

View related discussion on EngineerZone®

Recently Viewed