ADCLK854
RECOMMENDED FOR NEW DESIGNS1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer
- Part Models
- 2
- 1ku List Price
- Starting From $6.10
Part Details
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The ADCLK854 is a 1.2 GHz/250 MHz LVDS/CMOS fanout buffer optimized for low jitter and low power operation. Possible configurations range from 12 LVDS to 24 CMOS outputs, including combinations of LVDS and CMOS outputs. Three control lines are used to determine whether fixed blocks of outputs (three banks of four) are LVDS or CMOS outputs.
The ADCLK854 offers two selectable inputs and a sleep mode feature. The IN_SEL pin state determines which input is fanned out to all the outputs. The SLEEP pin enables a sleep mode to power down the device.
The inputs accept various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS. Table 8 provides interface options for each type of connection.
This device is available in a 48-pin LFCSP package. It is specified for operation over the standard industrial temperature range of −40°C to +85°C.
APPLICATIONS
- Low jitter clock distribution
- Clock and data signal restoration
- Level translation
- Wireless communications
- Wired communications
- Medical and industrial imaging
- ATE and high performance instrumentation
Documentation
Data Sheet 1
User Guide 1
Application Note 1
Technical Articles 3
Frequently Asked Question 1
Product Selection Guide 1
Tutorial 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| ADCLK854BCPZ | 48 ld LFCSP (7x7x.85mm w/2.8mm Pad) | ||
| ADCLK854BCPZ-REEL7 | 48 ld LFCSP (7x7x.85mm w/2.8mm Pad) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
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Feb 1, 2024 - 24_0009 Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process |
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| ADCLK854BCPZ | PRODUCTION | |
| ADCLK854BCPZ-REEL7 | PRODUCTION | |
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Jun 9, 2021 - 20_0126 Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea |
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| ADCLK854BCPZ | PRODUCTION | |
| ADCLK854BCPZ-REEL7 | PRODUCTION | |
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May 12, 2017 - 16_0077 Conversion of Select 4x4, 5x5, 6x6 and 7x7mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to ASE Korea. |
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| ADCLK854BCPZ | PRODUCTION | |
| ADCLK854BCPZ-REEL7 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
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ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Open ToolADCLK854 IBIS Models 2
Evaluation Kits
ADCLK854 Evaluation Board