AD9545

RECOMMENDED FOR NEW DESIGNS

Quad Input, 10-Output, Dual DPLL/IEEE 1588, 1 pps Synchronizer and Jitter Cleaner

Part Models
2
1ku List Price
Starting From $19.21
Viewing:

Part Details

  • Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks, providing frequency translation with jitter cleaning of noisy references
  • Complies with ITU-T G.8262 and Telcordia GR-253
  • Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2
  • Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb (5 × 10−8)
  • Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
  • Programmable digital loop filter bandwidth: 10−4Hz to 1850Hz
  • 2 independent, programmable auxiliary NCOs (1 Hz to 65,535 Hz, resolution < 1.37 × 10−12 Hz), suitable for IEEE 1588 Version 2 servo feedback in PTP applications
  • Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
  • Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported
  • 5 pairs of clock output pins with each pair usable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)
  • 2 differential or 4 single-ended input references
  • Crosspoint mux interconnects reference inputs to PLLs
  • Supports embedded (modulated) input/output clock signals
  • Fast DPLL locking modes
  • Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO
  • External EEPROM support for autonomous initialization
  • Single 1.8 V power supply operation with internal regulation
  • Built in temperature monitor and alarm and temperature compensation for enhanced zero delay performance
AD9545
Quad Input, 10-Output, Dual DPLL/IEEE 1588, 1 pps Synchronizer and Jitter Cleaner
AD9545 Functional Block Diagram AD9545 Pin Configuration
Add to myAnalog

Add product to the Products section of myAnalog (to receive notifications), to an existing project or to a new project.

Create New Project
Ask a Question

Documentation

Learn More
Add to myAnalog

Add product to the Products section of myAnalog (to receive notifications), to an existing project or to a new project.

Create New Project

Software Resources


Tools & Simulations

IBIS Model 1


Evaluation Kits

eval board
AD-GMSL2ETH-SL

FPGA-based 8x GMSL to 10 Gb Ethernet Adapter

Features and Benefits

  • Edge compute platform for machine vision and real-time sensor fusion for autonomous robots and vehicles applications
  • 8 x GMSL2 camera interfaces with up to 6 Gbps/channel
  • 10 Gbps SFP+ Ethernet interface
  • IEEE 1588 Precision Time Protocol for synchronization with host systems and other edge devices
  • Advanced embedded processing capabilities
  • ROS2 compliant
  • Advanced camera triggering functions and control features
  • Open-source software stack and FPGA design to enable custom applications development

Product Details

The AD-GMSL2ETH-SL is an edge compute platform enabling low-latency data transfer from eight Gigabit Multimedia Serial Link™ (GMSL) interfaces on to a 10 Gb Ethernet link. The target applications include autonomous robots and vehicles where machine vision and real-time sensor fusion is critical.

The system includes two MAX96724 Quad Tunneling GMSL2/1 to CSI-2 Deserializers, enabling connectivity to eight GMSL cameras. The video data from the cameras is transferred from the MAX96724 deserializers via MIPI CSI2 interfaces to an AMD KV26 System on Module which implements the logic to aggregate the video data from all the GMSL cameras into a 10 Gb Ethernet link, so that it can be sent to a central processing unit.

The IEEE 1588 Precision Time Protocol (PTP) with hardware timestamping is supported, enabling accurate synchronization with host systems and other edge devices. The AD9545 Quad Input, 10-Output, Dual DPLL/IEEE 1588, 1 pps Synchronizer and Jitter Cleaner is used to generate the required clocks for the 10 Gb Ethernet interface and the PTP logic.

A software networking stack can be used to realize the communication over the 10 Gb Ethernet link. Since the system runs Linux tools like gstreamer can be used to send the video data to a host and remote connection into the system is possible via ssh. The software network stack has limitations in terms of the maximum achievable transfer rate, and for this reason there is also the option to have an FPGA accelerated UDP or TCP implementation with Real Time Transfer (RTP) protocol for data packetization, which can get up to the maximum achievable data rate on the 10 Gb ethernet interface.

Accurate camera triggering control is achieved through dedicated FPGA logic, with configurable frequency and phase as well as selecting the trigger source between the internal logic and external signals.

Sixteen (16) general purpose I/O pins are available with software configurable functionality, operating at 3.3 V voltage level. A RS232 dedicated interface can be used to connect UART peripherals such as GNSS devices.

The design is accompanied by an open-source software stack and FPGA design, and reference applications, enabling custom software development to start from a proven implementation.

APPLICATIONS

  • Autonomous robots and vehicles

eval board
EVAL-AD9545

AD9545 Evaluation Board

Features and Benefits

  • Simple power connection using 6V wall adapter and on-board LDO voltage regulators.
  • 10 ac-coupled single-ended (differential signal recombined via a balun) output SMA connectors, with user-configurable output termination for HCSL, CML, or LVDS-compatible (default).
  • 4 configurable reference inputs, selectable between a single ended to differential reference input SMA connector.
  • 1 ac-coupled single-ended input SMA connector for system clock.
  • Pin programmable, power on ready configurability.
  • Status LEDs.
  • USB connection to PC.
  • Microsoft Windows-based evaluation software with simple graphical user interface via an ACE plug-in module
 

Product Details

The AD9545 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9545 dual digital PLL and 1 pps synchronizer. The AD9545 provides high-precision, multi-output clock generator functions, along with two on-chip jitter cleaning digital PLL cores. PLL0 and PLL1 are optimized for high performance synchronous clocking applications such as GPS, IEEE1588v2, Synchronous Ethernet, OTN, and next generation wireless baseband protocols. The PLLs are fully configurable via serial port control as well as configurable via an external EEPROM for power on ready configurations.

The AD9545 can output up to 5 differential clock signals, plus two single-ended clocks driven by a mix of two high performance digital PLLs, plus two high-precision NCOs (numerically controlled oscillators). 12 total outputs and 4 reference inputs are accessible on the evaluation board.

The output differential transmission line pairs use 50Ω single ended characteristic impedance and are connected to standard edge launch SMA connectors. The AD9545/PCBZ has a fully configurable power supply to allow the user to evaluate the AD9545 while being powered directly by a step down switching regulator or external LDOs. The AD9545 evaluation board uses RoHS-compliant FR-4 material. For convenience, detailed information from the AD9545 data sheet has been included here. Use the user guide in conjunction with the data sheet that has been provided by ADI.

eval board
AD-SYNCHRONA14-EBZ

Multichannel System Clocking Device

Features and Benefits

Processing System

  • Raspberry Pi 4, ARM Cortex-A72, 2GB SDRAM

User Interfaces

  • Gigabit Ethernet
  • 2 × USB 3.0 ports
  • 2 × USB 2.0 ports
  • SPI interface
  • GPIO
  • 2 bicolor LEDs
  • Male pin header

Clock Processing Devices

  • HMC7044 (High Performance, 3.2 GHz, 14-Output Jitter Attenuator)
  • AD9545 (1 PPS Synchronizer and Adaptive Clock Translator)

Clock Outputs

  • 4 x TWINAX LVPECL AC&DC coupled, 100Ω diff
  • 2 x SMA LVPECL AC coupled*
  • 4 x SMA CMOS*
  • 4 x SMA LVDS AC coupled*

*Configurable differential outputs, 50Ω diff

Clock Inputs

  • 3 differential 100Ω SMA clock inputs
  • PPS input
  • SYNC input
  • 10MHz input

Internal references

  • 100Mhz and 122.88Mhz Ultra-Low Phase Noise VCXO's (-165dBc/Hz)
  • 40Mhz and 38.4Mhz TCXO's (±1ppm) 50MHz OCXO(+/- 10ppb)
  • Internal references are software configurable

Power supply

  • DC 12V, 3A barrel jack

Product Details

The AD-SYNCHRONA14-EBZ is an ideal self-contained device to use in evaluation and prototyping of applications that need a highly accurate frequency and phase-controlled source clock. It is designed around the Analog Devices AD9545 and HMC7044 and greatly simplifies clock distribution and multi-channel synchronization in complex systems. It is intended to be used by trained professionals in a laboratory environment, and not intended as an end product for commercial use. It can be taken as a complete reference design and customised as required for any end customer applications. Full design details are made available free of charge.

The AD-SYNCHRONA14-EBZ comes in a 1U mechanical form factor. Using popular industry connector SMA and TwinAX interfaces most labs will already have the needed cables.

With its internal OCXO it can operate in standalone mode or be fed from a choice of external sources, such as 3 separate high speed differential clock inputs, a 10MHz reference and 1PPS. This flexibility combined with the capability to select either of the internal VCXO options of 100MHz or 122.88MHz, gives almost unlimited choice for the frequency of interest and accuracy needed for a wide variety of application areas. 

APPLICATIONS

  • High accuracy reference clock distribution
  • Systems clocked from a single source
  • Clocks derived from 100MHz or 122.88MHz
  • Phased Array Systems, RADAR, EW, SATCOMS, SDR
  • Bench Equipment
  • Remote controlled operation

AD-GMSL2ETH-SL
FPGA-based 8x GMSL to 10 Gb Ethernet Adapter
AD-GMSL2ETH-SL Board Photo Angle View AD-GMSL2ETH-SL Board Photo Top View AD-GMSL2ETH-SL Board Photo Bottom View AD-GMSL2ETH-SL Block Diagram
EVAL-AD9545
AD9545 Evaluation Board
AD9545ANGLE-web AD9545BOTTOM-web AD9545TOP-web
AD-SYNCHRONA14-EBZ
Multichannel System Clocking Device
AD-SYNCHRONA14-EBZ Evaluation Board - Front View AD-SYNCHRONA14-EBZ Evaluation Board Evaluation Board - Back View AD-SYNCHRONA14-EBZ Evaluation Board

Latest Discussions

Recently Viewed