AD9171
RECOMMENDED FOR NEW DESIGNSDual, 16-Bit, 6.2 GSPS RF DAC with Single Channelizer
- Part Models
- 2
- 1ku List Price
- Starting From $140.06
Part Details
- Supports single-band wireless applications
- 1 complex data input channel per RF DAC
- 516 MSPS maximum complex input data rate per input channel
- 1 independent NCO per input channel
- Proprietary, low spurious and distortion design
- 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output
- SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output
- Flexible 8-lane, 15.4 Gbps JESD204B interface
- Supports single-band use cases
- Supports 12-bit high density mode for increased data throughput
- Multiple chip synchronization
- Supports JESD204B Subclass 1
- Selectable interpolation filter for a complete set of input data rates
- 2×, 3×, 4×, and 6× configurable data channel interpolation
- 6× and 8× configurable final interpolation
- Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 3.1 GHz
- Transmit enable function allows extra power saving and downstream circuitry protection
- High performance, low noise PLL clock multiplier
- Supports 6.2 GSPS DAC update rate
- Observation ADC clock driver with selectable divide ratios
- Low power
- 1.45 W at 6 GSPS, single-channel mode
- 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch
The AD9171 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 6.2 GSPS. The device features an 8-lane, 15.4 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band direct to radio frequency (RF) wireless applications.
The AD9171 features one complex data input channels per RF DAC. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, frequency planning. The device supports up to a 516 MSPS complex data rate per input channel.
The AD9171 is available in a 144-ball BGA_ED package.
PRODUCT HIGHLIGHTS
- Supports one complex data input channel per RF DAC at a maximum complex input data rate of 513 MSPS with 12-bitresolution and 516 MSPS with 16-bit resolution options. There is one independent NCO per input channel.
- Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.
APPLICATIONS
- Wireless communications infrastructure
- Single-band base station radios
- Instrumentation, automatic test equipment (ATE)
Documentation
Data Sheet 1
User Guide 2
Technical Articles 1
Device Drivers 1
Analog Dialogue 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9171BBPZ | 144 ball (10x10x1.71 w/6.6 mm EP) | ||
| AD9171BBPZRL | 144 ball (10x10x1.71 w/6.6 mm EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Oct 22, 2021 - 19_0097 CANCELLED: Data Sheet and Die Revision for AD9171/AD9172/AD9173 |
||
| AD9171BBPZ | PRODUCTION | |
| AD9171BBPZRL | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 1
Evaluation Software 1
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
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Hardware Ecosystem
Tools & Simulations
ADIsimPLL™
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
Open ToolAD917X Remote Evaluation Tool
This tool gives users access to a live evaluation board in an Analog Devices lab, connected to a Keysight PXA spectrum analyzer and an ADS8-V1EBZ. The user is able to run tests on this remote lab bench to evaluate the AD9171/2/3 performance at any time, day or night. It is a great way to check performance of the product before and after purchase of an evaluation board, as well as to compare performance to a user-designed board.
Open ToolDAC Companion Transport Layer RTL Code Generator
These command line executable tool generates a Verilog module which implements the JESD204 transmitter transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
Open ToolS-Parameter 1
IBIS Model 1
Evaluation Kits
ADS8-V1 Evaluation Board
Resources
AD917x Evaluation Board