ADSP-21061
不推荐用于新设计50 MHz、150 MFLOPS、5v、浮点SHARC
产品详情
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The ADSP-21061 is a member of the powerful SHARC ® family of floating point processors. The SHARC ® Super Harvard Architecture Computerare signal processing microcomputers that offer new capabilities and levels of integration and performance.
The ADSP-21061 is a 32-bit processor optimized for high performance DSP applications. The ADSP-21061 combines the ADSP-21000 DSP core with a dual-ported on-chip SRAM and an I/O processor with a dedicated I/O bus to form a complete system-in-a-chip.
Fabricated in a high-speed, low-power CMOS process, the ADSP-21061 has a 20 ns instruction cycle time operating at 50 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.
The ADSP-21061 SHARC ® combines a high-performance floating-point DSP core with integrated, on-chip system features, including a 1 Mbit SRAM memory, host processor interface, DMA controller, serial ports and parallel bus connectivity for glueless DSP multiprocessing.
参考资料
数据手册 1
用户手册 1
应用笔记 40
处理器手册 2
集成电路异常 1
旧模拟器手册 2
评估工具包手册 1
这是最新版本的数据手册
软件资源
软件工具异常 1
Evaluation Software 0
工具及仿真模型
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