CN0188

The circuit is designed for a full-scale shunt voltage of 50 mV at maximum load current I_MAX. Therefore, the value of the shunt resistor is R_SHUNTM = (50 mV)/(I_MAX).

The "ground" for the op amp stage is connected to the common–mode source voltage (−48 V). The voltage for the op amp stage is supplied by the "floating" 5.6 V zener diode, which is biased at a current of approximately 2 mA. This eliminates the need for a separate power supply. The circuit will operate with a source voltage from −60 V to −10 V with no modifications.

The shunt voltage is amplified by a factor of 49.7 using U1A, where G = 1 + R3/R2. The zero-drift ADA4051-2 has a low offset voltage (15 μV maximum) and does not contribute significant error to the measurement. A full-scale shunt voltage of 50 mV produces a full-scale output voltage from U1A of 2.485 V (referenced to the common-mode source voltage).

An N-channel MOSFET transistor with a large VDS breakdown (70 V) inside the feedback loop of U1B applies the output voltage of U1A across resistor R5, and the resulting current flows through R6 and R7. The full-scale voltage from U1A of 2.485 V produces a full-scale current of 0.498 mA, which generates a full-scale voltage of 2.485 V across resistor R7. The voltage across R7 is applied to AIN− of the ADC. Resistor R6 and the Schottky diode D2 provide input protection for the AD7171 in the event the MOSFET shorts out.

Notice that the power supply voltage for the ADR381, the AD7171, and the floating zener diode is supplied by the isolated power output (+3.3 V_ISO) of the ADuM5402 quad isolator.

The reference voltage for the AD7171 is supplied by the ADR381 precision band gap reference. The ADR381 has an initial accuracy of ±0.24% and a typical temperature coefficient of 5 ppm/°C.

Although it is possible to operate both the AD7171 VDD and REFIN(+) from the 3.3 V power supply, using a separate reference provides better accuracy. A 2.5 V reference is chosen to provide sufficient headroom.

The input voltage to the AD7171 ADC is converted into an offset binary code at the output of the ADC. The ADuM5402 provides the isolation for the DOUT data output, the SCLK input, and the PDRST input.

The code is processed in the PC by using the SDP hardware board and LabVIEW software.

The graph in Figure 2 shows how the circuit tested achieves an error of 0.3% over the entire input voltage range (0 mV to 50 mV). A comparison is made between the code seen at the output of the ADC, recorded by LabVIEW, and an ideal code calculated based on a perfect system.

In order to calculate this ideal code, there are several assumptions which must be made about the performance of the system. First, the op amp gain stage must multiply the input signal by exactly 49.7. Depending on resistor tolerances (1%), this value will vary by 2% worst case. Secondly, the current sink resistor (R5) and the ADC input resistor (R7) are assumed to be identical. In the circuit, these particular resistors have a tolerance of 1%. Since they are the same value, the matching will probably be better than 1%. Resistors with tighter tolerances can be used, which will increase the accuracy and the cost of the circuit.

Several items have been implemented on the PCB, which are not crucial to the function or performance of the circuit but are required to ensure user and hardware safety. As an example, if Q1 breaks down or shorts out, the ADC, SDP board, user, and user’s PC are all at risk due to the large negative voltage potential. The safety items included are passive elements R6, D2, which protect the AD7171, and the ADuM5402 quadchannel digital isolator, which protects the circuits on the SDP board, as well as the user's PC.

PCB Layout Considerations

In any circuit where accuracy is crucial, it is important to consider the power supply and ground return layout on the board. The PCB should isolate the digital and analog sections as much as possible. This PCB was constructed in a four layer stack up with large area ground plane layers and power plane polygons. See the MT-031 Tutorial for more discussion on layout and grounding and the MT-101 Tutorial for information on decoupling techniques.

The power supply to the AD7171 and ADuM5402 should be decoupled with 10 μF and 0.1 μF capacitors to properly suppress noise and reduce ripple. The capacitors should be placed as close to the device as possible with the 0.1 μF capacitor having a low ESR value. Ceramic capacitors are advised for all high frequency decoupling.

Care should be taken in considering the isolation gap between the primary and secondary sides of the ADuM5402. The EVAL-CN0188-SDPZ board maximizes this distance by pulling back any polygons or components on the top layer and aligning them with the pins on the ADuM5402.

Power supply lines should have as large a trace width as possible to provide low impedance paths and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground.

A complete design support package for this circuit note, including board layouts, can be found at http://www.analog.com/CN0188-DesignSupport.