AD9523-1
RECOMMENDED FOR NEW DESIGNSLow Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
- Part Models
- 2
- 1ku List Price
- Starting From $11.13
Part Details
- Output frequency: <1 MHz to 1 GHz
- Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy)
- Zero delay operation
Input-to-output edge timing: <150 ps - Dual VCO dividers
- 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
- 14 dedicated output dividers with jitter-free adjustable delay
- Adjustable delay: 63 resolution steps of ½ period of VCO output divider
- Output-to-output skew: <50 ps
- Duty cycle correction for odd divider settings
- Automatic synchronization of all outputs on power-up
- Absolute output jitter: <150 fs at 122.88 MHz Integration range: 12 kHz to 20 MHz
- See data sheet for additional features
The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz.
The AD9523-1 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.
The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO.
An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.
APPLICATIONS
- LTE and multicarrier GSM base stations
- Wireless and broadband infrastructure
- Medical instrumentation
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
- Low jitter, low phase noise clock distribution
- Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
- Forward error correction (G.710)
- High performance wireless transceivers
- ATE and high performance instrumentation
Documentation
Data Sheet 1
User Guide 1
Application Note 1
Product Selection Guide 1
Device Drivers 1
Analog Dialogue 2
Webcast 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9523-1BCPZ | 72-Lead Lead Frame Chip Scale Package | ||
| AD9523-1BCPZ-REEL7 | 72-Lead Lead Frame Chip Scale Package |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Jun 26, 2023 - 23_0025 Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor |
||
| AD9523-1BCPZ | PRODUCTION | |
| AD9523-1BCPZ-REEL7 | PRODUCTION | |
|
Oct 13, 2015 - 15_0166 AD9523, AD9523-1, and AD9524 Specification Table Changes |
||
| AD9523-1BCPZ | PRODUCTION | |
| AD9523-1BCPZ-REEL7 | PRODUCTION | |
|
Jan 10, 2011 - 10_0351 AD9523-1 die revision |
||
| AD9523-1BCPZ | PRODUCTION | |
| AD9523-1BCPZ-REEL7 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 1
Evaluation Software 1
JESD204 Interface Framework
Integrated JESD204 software framework for rapid system-level development and optimization
Tools & Simulations
AD9523/AD9523-1 IBIS Model 1
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Open ToolEvaluation Kits
AD-FMCDAQ2-EBZ Evaluation Board
Resources
AD9523/AD9523-1 Evaluation Board
Resources
Software
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