Improvements in Stacked Load Architecture

Introduction

As load currents continue to increase in servers, especially in AI applications, while rail voltages tend to decrease, the conduction losses on the PCB become increasingly harmful. The concept of stacked power elements and processing of the power difference are considered possible solutions to this problem.^1–4 In particular, the energy exchanger concept was introduced by a previous study, where only the power difference is processed.¹ In this architecture, the average current is observed in the system rail, not the minimum current of the elements connected in series. As losses are generally proportional to the processed power, lowering the processed power generally leads to loss reduction. Notice that different converters can be used in the energy exchanger architecture, including different capacitor circuits.¹

Extending this concept to applications that need aggressive transient management, voltage regulators (VRs) are added to deal with the fast transient loads.^2–3 Regarding the low voltage, high current applications that target the AI market, a prototype board was built.⁴ The single-ended energy exchanger was implemented with switched capacitor circuits.³ As expected, the single-ended energy exchanger showed significant noise pollution of the load V_O rails when processing significant power difference. The reported measured system efficiency was ~86% at a full load of 250 W, with a predicted ~2% improvement if the bias circuits are improved.

Stacked Load System

This work presents a stacked load prototype that achieves >95% efficiency at a full load of 450 W. The critical improvement in the energy exchanger is also shown.

The block diagram of the stacked load prototype is shown in Figure 1. The main VR that is VR_total delivers full power to the stacked loads with the main objective to be as efficient as possible. The four fast VRs are responsible for the precise voltage regulation and transient response on each corresponding load rail. If loads are ideally matched, these fast VRs process zero power, and only if there is a load mismatch, they process power difference. The fast VRs are thermally designed for much smaller current than VR_total, as the maximum load difference is assumed to be smaller than the full load. However, it is important to design fast VRs to be capable of the full-scale transient of each load, because even if all loads are closely matched on average, it is hard to expect perfectly matched transient steps on all of them, and it takes longer time for the slower VR_total to adjust the output current.

The energy exchanger ensures power exchange among all the input rails for fast VR. If VR_total is driving only linear loads connected in series, the output current is determined by the lowest load current. But when the energy exchanger is added, the VR_total output current ideally becomes the averaged current between all loads. In practice, that current is slightly higher as it compensates for the losses in the fast VRs and energy exchanger.

Two different designs for the energy exchanger were evaluated: the originally considered single-ended energy exchanger shown in Figure 2 and the fully differential energy exchanger shown in Figure 3.

The single-ended energy exchanger from Figure 2 has a problem—return currents from each flying capacitor have to go through the C_O bulk capacitors of the loads in series. These charge-discharge currents have a much faster AC content compared to the output currents of the buck converters (both VR_total and fast VRs). Figure 4a shows the simulated system performance with the single-ended exchanger, when the load RL4 in Figure 1 has a current step of 50 A. There is a visible noise on all rails in general, which significantly increases when the energy exchanger starts moving the charge to the input of VR_4.

Fast transient loads were used to evaluate the dynamic performance, implemented by pluggable modules (only one plugged module for fast transient is shown in Figure 5). The main board also has connectors for the fast VRs. This arrangement allows easy adjustment and changes to the fast VR modules.

This noise problem appears to be fixed in Figure 4b, as the differential energy exchanger does not force any currents through the loads or C_O bypass of the load rails.

The implemented prototype for the stacked load system is shown in Figure 5. Two versions were designed with the only difference in the energy exchanger: one design with the single-ended solution from Figure 2, and the second with the differential exchanger from Figure 3.

Measured Results

The efficiency of the complete system operating with a balanced load, including all the bias circuitry from 12 V input and control, is shown in Figure 6. Load voltages were tested at 0.8 V, 0.9 V, and 1.0 V. The efficiency performance is very close between the two different energy exchanger options, EE1 and EE2, and in the nominal operating conditions, V_O = 4 V × 0.9 V = 3.6 V reaches more than 95% at full load. Notice that placing all loads in parallel corresponds to 500 A current into a single V_O = 0.9 V rail. Achieved >95% system efficiency noticeably outperforms published efficiency data for these conditions. High efficiency is driven by two main factors: 4× output current reduction as four loads are connected in series, and the main VR_total delivers full power into 4× higher V_STACK voltage (4 × V_O), as higher V_O generally improves VR efficiency.

While this is a prototype board with off-the-shelf parts and no optimization of components, the achieved high efficiency is in part credited to coupled inductors used in the main VR_total, as well as fast VR modules.

Generally, coupled inductors are allowed to keep switching frequencies low in a given reasonable size, keeping the switching loss down. This is especially important for the fast VRs, because in the case of balanced load, these VRs do not process much power, but still have switching losses that ideally need to be decreased.

The big difference in the operation of the two different energy exchangers is illustrated in Figure 7 and Figure 8, showing voltage ripple on the first V_O1 rail and VR1 input supply rail. The conditions for Figure 7 and Figure 8 are the same: V_O4 rail is loaded by I_O = 50 A, and all other rails are at zero current. So, the energy exchanger is moving a lot of power from the other rails to supply the rail V_O4. The single-ended energy exchanger drives large spikes through the parasitics of C_O on the VO1 rail⁴, while the differential energy exchanger just leaves the V_O rail intact, with only a small ripple at a much slower time scale that relates to the buck converter currents (not the switched capacitor circuits).

The most important impact is the reduction of the fast voltage spikes from >60 mV (>6.6% of VO = 0.9 V) in the case of the single-ended energy exchanger to <25 mV (<2.8% of VO = 0.9 V) in the case of the differential one. In the latter case, the voltage ripple has no high frequency spikes at all, only a ripple associated with the ripple current in the buck converters. The result matches the expected trend from the simulations. The fast spikes on the supply rail are potentially harmful to the digital circuitry and it is important to mitigate the issue. As VO values are expected to decrease further, the same amplitude of the noise has a larger impact on the operation of the fast loads.

Noise improvement is also implemented with the differential energy exchanger in Figure 3 by phase shifting among switching events for the different flying capacitors. Notice that it is not possible for the single-ended circuit in Figure 2; all capacitors must be switched at the same time.

Fast transient performance is shown in Figure 9, (a) loading and (b) unloading 100 A steps on rail V_O1. The other rails are unloaded. So, while initially the fast VR1 delivers all 100 A, the average 25 A comes from the VR total and the fast VR1 supplies only 75 A to the 100 A load. Looking at the changing droop on the V_O1 rail, notice that it takes approximately 10 μs for the VR_total to deliver 25 A average current, which decreases the fast VR1 droop proportionally. Correspondingly, VR2, VR3, and VR4 subtract 25 A from their rails and move that power into the energy exchanger and VR1. The energy exchanger voltages are unregulated. So, it takes longer than 10 μs to settle the input rail for the fast VR1 (yellow trace).

Conclusion

The fully functional stacked load prototype was implemented and showed efficiency generally higher than in traditional architectures for the same V_O and total P_O (>95% at V_O = 0.9 V at P_O = 450 W). The prototype board was made with off-the-shelf components, the actual optimization for customer specifications potentially led to even higher performance.

The concept of stacked load power delivery shows good promise in improving efficiency, as distribution losses are dramatically decreased and the main VR operates at a higher efficiency due to increased load voltage V_STACK. Notice also that the significant decrease in load current should bring more improvements in PCB losses when the loads are densely packed. In other words, actual customer application with very dense high current and low voltage load causes a bigger challenge for distribution losses. So, the improvement due to stacked load architecture is higher than on some prototype boards.

Building on the earlier developed energy exchanger concepts¹, the differential energy exchanger for floating rails showed much better noise behavior for the load voltage rails as any fast current and related voltage spikes were eliminated in any loading conditions.

References

¹ Anthony J. Stratakos and Alexandr Ikiannikov. “System, Method, Module, and Energy Exchanger for Optimizing Output of Series-Connected Photovoltaic and Electrochemical Devices.” U.S. Patent 9,331,499, April 2011.

² Enver Candan, Pradeep S. Shenoy, and Robert C. N. Pilawa-Podgurski. “A Series Stacked Power Delivery Architecture with Isolated Differential Power Conversion for Data Centers.” IEEE Transactions on Power Electronics, Vol. 31, No. 5, May 2016.

³ Shuai Jiang, Gregory Sizikov, and Mikhail Popovich. “Power Balancer for Series-Connected Load Zones of an Integrated Circuit.” U.S. Patent 10,985,652, March 2020.

⁴ K. Kshirsagar, D. Clavette, P. Kasturi, and W. Huang. “Power Loss Reduction in Power Distribution Network Through Vertical Stacking.” IEEE, June 2021.

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