What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs?

The clock distribution chips were designed with the intention to provide enough outputs to allow one output for each receive path. The best jitter performance requires a good match between the output and the driven input.

CMOS, of course, can drive multiple CMOS gates. However the number depends on the frequency of the clock, the capacitive loading (mostly parasitic), the termination, the input impedance of the driven devices, the input current (static) of the driven devices, the distance that the signal is being driven, the matching between paths, and probably even more factors. In general, though, a CMOS output can be expected to drive several CMOS (high impedance) devices, if the distances and parasitic loading is reasonable.

LVDS outputs can conceivably drive multiple loads, but this is not usually part of the language of LVDS. That is, since an LVDS output drives 3.5 mA through a 100 ohm termination load, it is probably OK to split the load into two 200 ohm resistors and drive two differential inputs which are in very close proximity. However, the potential for causing reflections on the 100 ohm differential transmission line is increased. This is not necessarily recommended, but is at least feasible.

LVPECL could also be expected to drive 2 or 3 differential inputs if the inputs are very close together. There are multiple ways of terminating the "far end" (that is, at the receivers). The "far end" termination must not be so heavy as to load down the driver much more than a single terminated receiver, but impedance matching to a transmission line can become very tricky. Of course, the "near end" termination must remain the same as is normally recommended – 180 to 200 ohms to ground on each side of the differential output to provide the path for the required amount of emitter current.