AN-1339: ADF7023-J AD_15d4g Firmware Download Module

Introduction

This application note describes the AD_15d4g firmware download module for the ADF7023-J transceiver IC. The AD_15d4g firmware download module adds the following features to the ADF7023-J:

• IEEE 802.15.4g physical layer (PHY) header formatting
• IEEE 802.15.4g data whitening
• Tx/Rx rolling data buffer
• 1 byte to 1000 byte Tx preamble
• ARIB STD T108 clear channel assessment (CCA)
• Rx antenna diversity

Figure 1 shows a block diagram of the ADF7023-J low power, 902 MHz to 958 MHz transceiver IC. The transceiver contains a custom microcontroller (MCU) core with a mask ROM, which implements packet handling functions and translates radio commands into internal control sequences. An additional 2 kB of program RAM (PRAM) is available and serves as program code memory. PRAM enables the addition of radio controller commands to provide modified or extended functionality. The AD_15d4g firmware download module described in this application note is based on program code downloaded into this PRAM.

The PRAM block is volatile memory and must be reloaded each time the transceiver wakes up from sleep state. The PRAM locations can be accessed sequentially through the serial peripheral interface (SPI) interface. The details of the code download mechanism are explained in the Code Download Sequence section.

The firmware download binary is rom_ram_7023_2_2_AD_ 15d4g_R4p3.dat and is available from Analog Devices, Inc., at ftp://ftp.analog.com/pub/RFL/FirmwareModules.

The AD_15d4g firmware download module remaps several of the ADF7023-J registers and commands and extends the data sheet state diagram. See the Register Remapping section for more information.

Note that throughout this application note, multifunction pins, such as the ADCIN_ATB3 pin, are referred to either by the entire pin name or by a single function of the pin, for example, ATB3, when only that function is relevant.

Register Remapping

The firmware extends the ADF7023-J data sheet state diagram to include the 15d4g state, as outlined in Figure 2, and extends the firmware states, as defined in Table 3.

When the firmware module is downloaded and the 15d4g state is entered, some of the battery backup random access memory (BBRAM) registers take on new meaning, and some are rendered redundant. The remapped BBRAM registers are defined in Table 1. The command list is expanded, as defined in Table 2. The INTERRUPT_MASK_0 register and the INTERRUPT_ SOURCE_0 register are also remapped while in the 15d4g state, as defined in Table 29 and Table 30.

Packet RAM locations 0x20 to 0xFF are available for packet data in the 15d4g state. Bytes 0x00 to 0x1F are allocated for use by the on-chip processor and must not be used for packet data.

When 15d4g state is exited, all normal data sheet functionality is restored. Note, however, that the reused settings must be reprogrammed appropriately according to the data sheet.

Register Map Extension

Register Descriptions

The values in Address 0x132 (the BB_PHR_LOW register) are read only. In receive mode, the values are copied in by the AD_15d4g firmware download module from a received packet. In transmit mode, the required PHR value for a transmit must be written to the TX_BASE_ADR register and the firmware reflects those values back in Address 0x132.

The values in Address 0x133 (the BB_PHR_HIGH register) are read only. In receive mode, the values are copied in by the AD_15d4g firmware download module from a received packet. In transmit mode, the required PHR value for a transmit must be written to the TX_BASE_ADR register and the firmware reflects those values back in Address 0x133

Interrupt Mask and Source Configurations

Antenna Signal Path Control

The ATB1, ATB2, ATB3, and ATB4 pins on the ADF7023-J are used to control the radio frequency (RF) antenna diversity switches. This section provides configuration details for these four pins in receive and transmit modes.

Receive Mode

In PHY_RX_CCA_15d4 state, the mapping of the control bits to configure the antenna signal paths is automatically controlled by Bits[7:6] and Bits[5:4] of the BB_RX_ANTENNA_DIVERSITY_ CFG register (Address 0x129). Bits[7:6] control the signal path for Antenna 0, as shown in Table 31, and Bits[5:4] control the signal path for Antenna 1, as shown in Table 32.

With antenna diversity enabled (Address 0x129, Bit 0 = 1), the ADF7023-J automatically toggles between the two antennas.

With antenna diversity disabled (Address 0x129, Bit 0 = 0), the device uses the value programmed into Address 0x129, Bit 1 (the ANTENNA_SLECTED bit) to select which antenna and antenna path to use.

These control bits appear at the ATB1 and ATB2 pins as V_DD control bits, or at the ATB3 and ATB4 pins as 1.8 V control bits. The selection between V_DD or 1.8 V controls is made using the RX_ATB_LEVEL bit, Bit 3 of the BB_RX_ANTENNA_DIVERSITY_CFG register.

Transmit Mode

For transmit mode, the transmit path is automatically controlled by Bits[7:6] and Bits[5:4] of the BB_TX_ANTENNA_CFG register (Address 0x12A). Bits[7:6] control the signal path for Antenna 0, as shown in Table 31, and Bits[5:4] control the signal path for Antenna 1, as shown in Table 32.

The selection of which antenna to use for Tx is controlled by the TX_ANTENNA bit (Bit 1 of Address 0x12A). Setting the TX_ANTENNA bit to 0 selects Antenna Path 0 for Tx, and setting it to 1 selects Antenna Path 1 for Tx.

These control bits appear at the ATB1 and ATB2 pins as V_DD control bits, or at the ATB3 and ATB4 pins as 1.8 V control bits. The selection between V_DD or 1.8 V controls is made using the TX_ATB_LEVEL bit, Bit 3 of the BB_TX_ANTENNA_ CFG register.

Fast Tx/Rx Transitions

The AD_15d4g firmware download module supports fast transitions from the PHY_ON_15d4 state to the PHY_TX_ 15d4 state and the PHY_RX_CCA_15d4 state. The fast transitions are achieved by the following sequence:

1. Issue the CMD_SYNTH_CAL_15d4 command (Command 0xEE) while in the PHY_ON_15d4 state. A synthesizer calibration is performed at the programmed channel frequency, and the results are stored in the BB_VCO_BAND_READBACK register (Address 0x13B) and the BB_VCO_AMP_READBACK register (Address 0x13C).
2. Enable synthesizer calibration overwrite by setting VCO_OVRW_EN (Address 0x3CD) to 0x3.

The CMD_PHY_RX_CCA_15d4 command and the CMD_ PHY_TX_15d4 command complete in a shorter time after this sequence, because a synthesizer calibration is no longer performed.

Note that it is good practice to periodically perform a full synthesizer calibration. A full synthesizer calibration maintains optimum RF performance across fluctuations in operating temperature or battery voltage.

Antenna Diversity

In addition to propagation loss, channel impairments, such as multipath and signal fading, can degrade the performance and robustness of a wireless communication link.

The propagation of an electromagnetic wave is subject to impairments such as reflections, refractions, and scattering along its path, as illustrated in Figure 3. At the input to a receiver, multiple copies of the transmitted signal can arrive at slightly different times and have varying amplitudes. These multipath signals superimpose and result in constructive or destructive interference in the composite signal seen at the input to the receiver.

To combat this issue, antenna diversity techniques can be used to improve the performance of the radio link. By measuring the signal quality from two antennas that are physically separate, the antenna with the highest quality signal can be directed to the input of the receiver. By physically separating the antennas, the probability that both antennas suffer the same fading characteristics at the same time is significantly reduced.

The technique employed by the ADF7023-J firmware download is a switched diversity technique. In receive mode, an external RF switch (for example, a double pole, double throw (DPDT) switch) is used to select a signal from one of two antennas, as shown in Figure 4. The ATB1 and ATB2 pins provide logic control of the RF diversity switch from the ADF7023-J. The ADF7023-J also offers the flexibility to assign any combination of logic states (00, 01, 10, 11) to the switch control pins, ATB1 and ATB2. This configurable polarity scheme supports control of a wide range of RF switch topologies. The maximum logic output level from the ATB1 and ATB2 pins is V_DD. If 1.8 V logic levels are required, use the ATB3 and ATB4 pins. See the Antenna Signal Path Control section for more details on the configuration of these pins.

The ADF7023-J evaluates the quality of the received signal from either antenna by the use of a dual qualification process: by qualifying the existence of a valid preamble sequence (101010…) and by measuring the power level (RSSI). This two-level qualification process ensures high quality signal integrity at the input to the receiver and ensures sufficient signal-to-noise ratio (SNR) for packet reception.

After a packet is received, if continuous Rx is enabled (Address 0x139, Bit 0 = 1), the ADF7023-J remains in receive mode with the algorithm continuing to evaluate signal quality from both paths. If continuous Rx is not enabled, the ADF7023-J returns to the PHY_ON_15d4 state after packet reception.

The diversity algorithm is most effective at input power levels close to the sensitivity level of the receiver. In such conditions, if antenna diversity is not used, the packet error rate (PER) performance of the receiver can be significantly degraded due to multipath and signal fading loss. With diversity enabled, the likelihood of fading occurring on both antennas at the same time is significantly diminished and the ADF7023-J firmware automatically selects an antenna with the highest SNR.

Antenna Diversity Algorithm

Antenna diversity is enabled by setting Bit 0 of the BB_RX_ ANTENNA_DIVERSITY_CFG register (Address 0x129) to 1.

Upon entering the PHY_RX_CCA_15d4 state with antenna diversity enabled, the signal on each antenna is evaluated, switching between antennas with a fixed search timer period.

The algorithm operates as follows:

• The ADF7023-J performs both preamble qualification and RSSI measurement on both antennas. During preamble qualification, the received bit stream is correlated against a fixed number of 10 preamble bit pairs in the ADF7023-J.
• RSSI measurement is also performed during this search period.
• After the antenna search period has expired, the same preamble qualification and RSSI measurement is performed on the second antenna.
• When a valid preamble sequence is detected on both antennas, the antenna with the largest RSSI reading is used for reception.
• When a valid preamble sequence is detected only on one antenna, this antenna is selected for reception of the packet.
• If the preamble sequence is not qualified on either antenna, the algorithm continues to switch between both antennas at the search period rate.

After completing packet reception, if the BIT_CONTINUOUS_ RX bit, Bit 0 of the BB_TESTMODES register (Address 0x139), = 1, the device returns to the PHY_RX_CCA_15d4 antenna search state and the diversity algorithm continues to evaluate both antennas. Note that as the device transitions back to the PHY_ RX_CCA_15d4 state, the interrupts are not automatically cleared (see Figure 5).

If the BIT_CONTINUOUS_RX bit = 0, the device returns to the PHY_ON_15d4 state at the end of packet reception, and the identification of the antenna selected can be read back from the value in Bit 1 of the BB_RX_ANTENNA_DIVERSITY_CFG register.

The Antenna RSSI values can be read back from Address 0x12B (Antenna 0) and Address 0x12C (Antenna 1) (see Figure 6).

The mapping of the control bits to configure the antenna paths is programmable in Bits[7:6] and Bits[5:4] of the BB_RX_ ANTENNA_DIVERSITY_CFG register (Address 0x129).

These control bits appear at the ATB1 and ATB2 pins as V_DD logic levels, or at the ATB3 and ATB4 pins as 1.8 V logic levels. Select between V_DD or 1.8 V levels using the RX_ATB_LEVEL bit, Bit 3 of the BB_RX_ANTENNA_DIVERSITY_CFG register (Address 0x129).

See the Antenna Signal Path Control section for more details.

Performance in a Fading Environment

The performance of this algorithm was measured under the following conditions:

• Preamble length = 10 bytes
• Payload length = 12 bytes
• Data rate = 100 kbps
• Modulation index = 1
• Rayleigh fading
• Fading pitch = 4 Hz
• Correlation between antennas: 0% and 100% (100% correlation is equivalent to the single antenna case in a fading environment)

Under these conditions, a diversity gain of >9 dB was achieved at the 1% PER point (see Figure 7).

Clear Channel Assessment

For clear channel assessment, the CCA threshold is programmed into the BB_CCA_THRESHOLD register (Address 0x105). If the measured RSSI is above this threshold, the channel is busy. If the measured RSSI is below this threshold, the channel is clear.

Evaluation of CCA and RSSI is automatically activated upon entering the PHY_RX_CCA_15d4 state. Multiple times per byte, the RSSI value is evaluated, and the CCA_LIVE_STATUS flag is updated to busy or clear. Thus, after entering the PHY_RX_CCA_ 15d4 state, the RSSI value and a live CCA status are always updated unless updates are turned off with the CCA_BYPASS_UPDATE bit (Bit 0 of Address 0x103).

Note that there is a time lag until the first RSSI value is updated upon first entering the PHY_RX_CCA_15d4 state. Until the first RSSI value is updated, the previously measured RSSI value is retained. To clear the previously measured RSSI value, the BB_ANTENNA0_RSSI and BB_ANTENNA1_RSSI registers can be zeroed before entering the PHY_RX_CCA_15d4 state.

The ADF7023-J firmware download module can support CCA and antenna diversity at the same time.

When antenna diversity is enabled, the RSSI value on the current antenna is evaluated multiple times every byte, while the value on the alternate antenna is held at its last measured value. When the antenna switches, the RSSI on the deselected antenna is held, and the RSSI on the currently selected antenna is updated. The CCA_LIVE_STATUS bit is updated continuously to signify if the measured RSSI is above or below the CCA threshold. Any excursion above the CCA threshold sets the CCA_STATUS bit to busy.

When antenna diversity is not enabled, only the RSSI on the current antenna is evaluated and compared with the CCA threshold to determine if the channel is busy or clear, and update the CCA_STATUS flag accordingly.

There are two distinct modes of operation: timer mode and infinity mode. These modes are discussed in the CCA Timer Mode section and the CCA Infinity Mode section.

CCA Timer Mode

CCA timer mode is used with automatic Tx (the BB_CCA_ CFG_0 register, Bit 4 = 0), and is initiated by the CMD_CCA_ START command.

In timer mode, the CCA evaluation period is programmable in CCA_TIMER in the BB_CCA_CFG_0 register. This is a timer in µs, as defined in Table 33.

In timer mode, the timer is initiated and the evaluation period is started by the CMD_CCA_START command. When the timer times out, or the timer is interrupted by an incoming packet, the CCA interrupt is generated (if it is enabled). Note that there is an internal overhead on the timer mode, which means the CCA evaluation period is somewhat less than the CCA timer value. In particular, for the 160 µs timer, under certain conditions, the CCA evaluation time is less than 128 µs. Therefore, it is recommended that, if Timer 000 is used, users perform their own characterization tests to ensure performance, per TELEC requirements.

The CCA_STATUS bit is automatically cleared at the beginning of every evaluation period (channel free). If the CCA_LIVE_ STATUS bit goes high (becomes busy) at any stage during the evaluation period, the CCA_STATUS flag is automatically updated to busy.

CCA timer mode is used with automatic Tx (the BB_CCA_ CFG_0 register, Bit 4 = 0) only. If the channel is clear, and automatic Tx is enabled, the device transitions automatically to the PHY_TX_15d4 state (see Figure 8).

If the channel is busy and the timer times out, a CCA interrupt is generated, and the device remains in the PHY_RX_CCA_ 15d4 state, with the CCA_STATUS bit set to busy (see Figure 9).

It is important to note that the RSSI value is continuously updated and evaluated during each byte period. Therefore, in antenna diversity mode, to ensure that both antennas are evaluated before making a CCA judgment, the CCA timer must be ≥4 bytes.

During CCA timer mode, incoming packets can be received.

If an SFD is detected on the best antenna, any running CCA timer is terminated and the CCA interrupt is asserted after SFD detection. The CCA_STATUS bit is set to busy. The packet continues to be received normally (see Figure 10).

If the CCA timer times out during the preamble or SFD of an incoming packet, that packet is lost and the CCA interrupt is generated (see Figure 11).

Issuing Commands During Packet Reception

Take care when issuing the CMD_CCA_START command because there are certain conditions under which issuing the command, coincident with the start of preamble on an incoming packet, causes that packet to be lost. Minimizing this risk is discussed in the Potential Packet Loss When Issuing Commands section.

Dynamic IF Filter Bandwidth Setting During CCA Timer Mode

The functionality of the intermediate frequency (IF) filter bandwidth for Rx during CCA timer mode is discussed in this section.

Upon entering the PHY_RX_CCA_15d4 state, the receiver baseband filter bandwidth is selected from the BBRAM (Bits[7:6] of Address 0x115).

In CCA timer mode, the receiver baseband filter can be automatically changed for CCA RSSI by setting the ENABLE_ IFBW_AUTO_SWITCH bit (Bit 5 of the CCA_CFG_1 register, Address 0x104) to 1. Then, the filter bandwidth automatically switches to the CCA_FILTER_BW bit setting (Bits[6:5] of the BB_CCA_CFG_0 register, Address 0x103) when the CMD_ CCA_START command (Command 0xB7) is issued.

Note that the IF of the receiver can toggle between 200 kHz and 300 kHz depending on the selected filter bandwidth.

The IF filter bandwidth of the receiver is switched back to its original BBRAM setting (Bits[7:6] of Address 0x115) on the occurrence of one of the following events:

• If the CCA timer times out
• Upon issuing the CMD_CCA_STOP command
• Upon issuing the CMD_PHY_RX_CCA_15d4 command
• Upon an incoming packet preamble detection if the ENABLE_IFBW_SWITCH_ON_PREAMBLE bit = 1

Upon an incoming packet preamble detection, if the ENABLE_ IFBW_SWITCH_ON_PREAMBLE bit = 1, the receiver baseband filter switches back to its original value for packet reception (see Figure 12).

Upon an incoming packet preamble detection, if the ENABLE_ IFBW_SWITCH_ON_PREAMBLE bit = 0, the receiver baseband filter bandwidth is retained at its current value for the duration of the packet reception, and switches back at the end of packet reception.

False Preamble Detection During CCA Timer Mode

If a false preamble is detected while in CCA timer mode and the ENABLE_IFBW_SWITCH_ON_PREAMBLE bit = 1, the receiver switches back to its original value for packet reception (as specified in the IFBW bits (Bits[7:6] of Address 0x115)).

If SFD is subsequently not detected, this is a false preamble detection, and the firmware takes the following action:

• If the ENABLE_IFBW_AUTO_SWITCH bit = 1, the ADF7023-J sets the IF filter bandwidth to the CCA_FILTER_BW bit setting (Bits[6:5] of the BB_CCA_CFG_0 register, Address 0x103) as soon as SFD is not detected.
• If the ENABLE_IFBW_AUTO_SWITCH bit = 0, the ADF7023-J sets the IF filter bandwidth to the original IFBW bit setting for packet reception, as specified in the IFBW bits (Bits[7:6] of Address 0x115) as soon as SFD is not detected.

If a false preamble is detected while in CCA timer mode, and the ENABLE_IFBW_SWITCH_ON_PREAMBLE bit = 0, the receiver does not switch back during preamble.

If SFD is subsequently not detected, this is a false preamble detection, and the firmware takes the following action:

• If the ENABLE_IFBW_AUTO_SWITCH bit = 1, the ADF7023-J sets the IF filter bandwidth to the CCA_ FILTER_BW bit setting (Bits[6:5] of Address 0x103) as soon as SFD is not detected.
• If the ENABLE_IFBW_AUTO_SWITCH bit = 0, the ADF7023-J sets the IF filter bandwidth to the original IFBW value for packet reception, as specified in the IFBW bit (Bits[7:6] of Address 0x115) as soon as SFD is not detected.

CCA Infinity Mode

CCA infinity mode is used with manual Tx (the BB_CCA_ CFG_0 register, Bit 4 = 1).

Setting CCA_TIMER to 7 (binary code 111), initiates infinity mode. To select a wider IF filter for CCA during infinity mode, the CMD_CCA_FILTER command must be issued before setting CCA_TIMER to 7. Therefore, when transitioning from the PHY_ON_15d4 state, set the timer value to a value other than infinity. Upon entering Rx, the CMD_CCA_FILTER command can be issued, followed by setting the timer value to infinity. The operation of the IF bandwidth switching for infinity mode is discussed in the Dynamic IF Filter Bandwidth Setting During CCA Infinity Mode section.

As soon as infinity mode is initiated, the ADF7023-J continues to evaluate the channel until the channel is clear (see Figure 13 and Figure 14).

In infinity mode, the ADF7023-J only generates a CCA interrupt when the channel is clear for a minimum of 128 µs. If the channel is clear, the device generates an INTERRUPT_CCA interrupt, stays in the PHY_RX_CCA_15d4 state, and reverts the IF filter back to its default value while still evaluating CCA RSSI and updating the CCA_LIVE_STATUS flag.

Note that if the channel remains clear, and the CCA interrupt is cleared, it is reasserted after another 128 µs evaluation period. To avoid reasserting the channels, the CCA interrupt can be masked, or infinity mode can be exited, by setting CCA_TIMER to a value other than 7 before clearing the interrupt.

Infinity mode is used with manual Tx, so automatic Tx must be disabled for infinity mode.

If infinity mode is used with antenna diversity enabled, both antennas must be clear before the channel is considered clear and the interrupt is generated. In this case, the CCA time increases to a minimum of 250 µs (see Figure 15).

During CCA infinity mode, any incoming packet can be received. If continuous Rx is enabled, the device returns to the PHY_RX_CCA_15d4 state with infinity mode still enabled. However, if the ENABLE_IFBW_SWITCH_ON_PREAMBLE bit is enabled (1), the CCA filter bandwidth reverts to its default Rx value on preamble detection. If continuous Rx is enabled, the filter bandwidth is reverted to the CCA filter bandwidth by reissuing the CMD_CCA_FILTER command.

If continuous Rx is not enabled, the device returns to the PHY_ON_15d4 state upon packet reception.

Dynamic IF Filter Bandwidth Setting During CCA Infinity Mode

Upon entering the PHY_RX_CCA_15d4 state, the receiver baseband filter bandwidth is selected from the BBRAM (Bits[7:6] of Address 0x115).

Setting CCA_TIMER to 7 (binary code 111), initiates infinity mode. To select a wider IF filter for CCA during infinity mode, the CMD_CCA_FILTER command (Command 0xB9) must be issued before setting CCA_TIMER to 7.

After the user issues the CMD_CCA_FILTER command (Command 0xB9), the bandwidth is automatically adjusted to the desired setting in Bits[6:5] of BBRAM Address 0x103 and Rx is restarted to allow synchronization of the antenna search period with the new setting (Figure 16).

Take care when issuing the CMD_CCA_FILTER command because there are certain conditions under which issuing the command, coincident with the start of preamble on an incoming packet, causes that packet to be lost. To minimize this risk, see the Potential Packet Loss When Issuing Commands section for more information.

Note that the IF of the receiver can toggle between 200 kHz and 300 kHz depending on selected filter bandwidth.

The IF filter bandwidth of the receiver is reverted back to its original BBRAM setting (Bits[7:6] Address 0x115) under of the following conditions:

• Upon issuing the CMD_CCA_STOP command (Command 0xB8)
• Upon issuing the CMD_PHY_RX_CCA_15d4 command (Command 0xB2)
• Upon an incoming packet preamble detection if the ENABLE_IFBW_SWITCH_ON_PREAMBLE bit = 1

Upon an incoming packet preamble detection, if the ENABLE_ IFBW_SWITCH_ON_PREAMBLE bit = 1, the receiver baseband filter switches back to its original value for Rx.

If the ENABLE_IFBW_SWITCH_ON_PREAMBLE bit = 0 , the receiver baseband filter bandwidth is retained at its current CCA value for the duration of the packet reception.

False Preamble Detection During CCA Infinity Mode

Note that a false preamble detection reverts the filter back to its default Rx value. By enabling the preamble detect interrupt, this condition can be alerted to the user. The filter returnsto the desired CCA filter value by reissuing the CMD_CCA_FILTER command.

Alternatively, Bit 0 in the PHY_RX_STATUS register (Address 0x01F) can be monitored to alert when a preamble has been detected and revert the filter to its previous CCA value if no SFD interrupt is received.

Command Access During the PHY_RX_CCA_15d4 STATE

The ADF7023-J is controlled through commands, and command access is described in the ADF7023-J data sheet. The ADF7023-J data sheet also describes the use of the status word to ensure the communications processor is ready to accept a new command.

Potential Packet Loss when Issuing Commands

Take care when issuing commands in the PHY_RX_CCA_15d4 state while waiting for an incoming packet because of the asynchronous timing of the incoming packets.

There are certain conditions under which issuing a command, coincident with the start of preamble on an incoming packet, causes that packet to be lost. Commands involved are the following:

• CMD_PHY_RX_CCA_15d4
• CMD_PHY_TX_15d4
• CMD_PHY_ON_15d4
• CMD_CCA_START
• CMD_CCA_FILTER

To minimize this risk of losing an incoming packet, a PHY_ RX_STATUS byte (Address 0x01F) is offered (see Figure 17). Bit 0 of this byte highlights when a preamble is detected, and Bit 1 indicates when the SFD is detected.

Upon entering the PHY_RX_CCA_15d4 state, Bit 0 and Bit 1 of the PHY_RX_STATUS register (Address 0x01F), are set to 0. Upon preamble detection, Bit 0 is set to 1. Upon SFD detection, Bit 1 is set to 1. At the end of packet reception, both bits are set back to 0 (see Figure 18). If a false preamble is detected (for example, a qualified preamble without a subsequent SFD), these bits are set to 0 and the search for a preamble continues.

Packet loss can be minimized by monitoring the PHY_RX_ STATUS register and issuing commands only when the PHY_RX_STATUS register = 0.

However, monitoring the PHY_RX_STATUS register method, there is still a condition under which packet loss is possible where a preamble may have started in the air, but is not yet detected by the device.

The two extremes of this condition are outlined in Figure 19 and Figure 20. The worst case scenario occurs at the latest possible preamble qualification time during antenna diversity, which is 8 bytes into the 10-byte preamble (see Figure 19). In this scenario, if a command (for example, the CMD_CCA_START command) occurs during the first eight bytes of preamble, it disrupts the preamble acquisition and may cause packet loss. The best case scenario occurs at the earliest possible preamble qualification time, which is three bytes into preamble (see Figure 20). In this case, if the CMD_CCA_START command occurs during the first three bytes of preamble, there may be packet loss.

Packet Structure in 15d4 Mode

The ADF7023-J AD_15d4g firmware download module supports the MR_FSK PPDU header format without mode switching.

The packet structure is displayed in Figure 21.

In transmit mode, the ADF7023-J firmware download module adds the requested number of preamble bytes, and then inserts the requested SFD and PHR. If whitening is enabled, the PSDU is whitened. If a 16-bit FCS is enabled, the 16-bit CRC is automatically calculated and appended to the transmit payload.

In receive mode, the preamble optionally generates a preamble detect interrupt, and is not stored to the packet RAM. The SFD is used for byte level synchronization, optionally generates an interrupt synchronous with PHR reception, and is not stored to the packet RAM. PHR is received next, and, depending on its contents, dictates the receive packet length, whether dewhitening is to be applied or not, and whether or not FCS bytes are validated (the 16-bit FCS case is handled). Dewhitening is required in Rx if whitening is applied in Tx.

Preamble

Preamble is a 1010 sequence added to the start of the packet during transmission, and removed after receiving the packet. Preamble length is defined in bytes, with a programmable range of 4 bytes to 1000 bytes. It is configured by writing to the BB_NB_ PREAMBLE_BYTES_HIGH register (Address 0x12F) and the BB_NB_PREAMBLE_BYTES_LOW register (Address 0x12E).

SFD

SFD is a 2-byte word that is controlled by writing to the BB_SFD_ HIGH register (Address 0x131) and the BB_SFD_LOW register (Address 0x130). The SFD takes on one of four valid options selected from Table 34. Note that the SFD is transmitted starting from Bit 0.

PHR

PHR is a 2-byte word, as defined in the PHR section in Figure 21. This word is controlled by writing the low byte to the TX_BASE_ ADR register, and the high byte to the address value, TX_BASE_ ADR + 1, because these form the first two bytes of the transmit packet. After issuing the CMD_PHY_TX_15d4 command, the contents of these two bytes are copied into the BB_PHR_LOW (Address 0x132) and BB_PHR_HIGH (Address 0x133)registers, respectively. Likewise, upon successful packet reception, the packet header bytes are copied into the BB_PHR_LOW register and the BB_PHR_HIGH register.

The following sections detail the PHR bit definitions: mode switch, reserved, FCS, whitening, and length.

Mode Switch

Bit 7 of the BB_PHR_LOW register is the MODE_SWITCH bit. The MODE_SWITCH bit is set to 0, indicating there is no data rate or modulation scheme change during the packet transmission. If the ADF7023-J receives a packet with mode switch the MODE_ SWITCH bitset to 1, it does not generate a PHR interrupt, but does generate an INTERRUPT_CRC_CORRECT interrupt and INTERRUPT_RX_EOF interrupt (if they are enabled).

Reserved

The BB_PHR_LOW register, Bits[6:5], are reserved. The reserved bits are set to 0 for the ADF7023-J firmware for transmit mode, and are ignored by the ADF7023-J firmware download module in receive mode.

FCS

Bit 4 of the BB_PHR_LOW register is the FCS bit.

FCS = 0 indicates a 32-bit FCS. This case is not handled automatically by the ADF7023-J firmware download module. For transmit, the user must calculate the 32-bit CRC and add it to the PSDU. In receive mode, the 32-bit CRC is received as part of the PSDU and stored in the packet RAM, CRC is not validated, and the CRC interrupt is not asserted. The INTERRUPT_RX_EOF interrupt indicates when the packet is received.

FCS = 1 indicates a 16-bit CRC. This case is handled automatically by the firmware. In transmit mode, the 16-bit CRC is calculated and appended to the transmit PSDU. In receive mode, the 16-bit CRC is calculated from the incoming payload and, if the CRC is correct, the CRC interrupt is asserted (if enabled).

Whitening

Bit 3 of the BB_PHR_LOW register is the whitening bit. If the whitening bit = 0, the PSDU is not whitened, and if the whitening bit = 1, the PSDU is whitened on transmission. Only the PSDU is whitened, not the SFD or PHR.

In receive mode, if the whitening bit is set to 1 in the received packet header, the ADF7023-J firmware download module automatically dewhitens the received PSDU.

Length

Bits[2:0] of the BB_PHR_LOW register define Bits[10:8] of the PSDU_LENGTH[10:0] word, and Bits[7:0] of the BB_PHR_ HIGH register define Bits[7:0] of the PSDU_LENGTH[10:0] word.

The PSDU_LENGTH[10:0] word can be set to values in the range of 3 to 2047.

Tx/Rx Rolling Data Buffer

In packet mode, when the ADF7023-J receives a packet, the data is stored in a linear sequence in the packet RAM. Prior to transmission, the data to be transmitted is written to the packet RAM in a linear sequence. This functionality is described in the ADF7023-J data sheet.

If the AD_15d4g firmware download module is used, it is possible to receive or transmit packets that are longer than the available packet RAM, which is accomplished via a rolling buffer. The registers applicable to the operation of the rolling buffer are given in Table 35.

Packet RAM locations 0x20 to 0xFF are available for packet data. Bytes 0x00 to 0x1F are allocated for use by the on-chip processor and must not be used for packet data.

Rolling Buffer in Transmit Mode

In transmit mode, the TX_BASE_ADR registersets the start of the rolling buffer in packet RAM. The BB_TX_BUFFER_SIZE register sets the size of the buffer. Do not allow the buffer size to exceed the available packet RAM. When the value in the BB_TX_BUFFER_ SIZE register is added to the value in the TX_BASE_ADR register, do not exceed Address 0x0FF.

Set the value in the BB_TX_BUFFER_SIGNAL register so that an INTERRUPT_BUFFER_ALMOST_FULL interrupt is generated prior to transmission of all the data in the buffer. Typically, the BB_TX_BUFFER_SIGNAL register is set so the interrupt is asserted when half of the data in the buffer has been transmitted.

When an INTERRUPT_BUFFER_ALMOST_FULL interrupt is asserted, the host microprocessor writes new data to the locations from address value TX_BASE_ADR to address value, TX_BASE_ADR + BB_TX_BUFFER_SIGNAL.

When the data in the last byte of the Tx buffer has been transmitted, the ADF7023-J continues transmitting, starting with the data at the address value TX_BASE_ADR. If enabled, an INTERRUPT_BUFFER_FULL interrupt is asserted when the last byte in the buffer is transmitted.

When an INTERRUPT_BUFFER_FULL interrupt is asserted, the host microprocessor writes new data to the locations from address value, TX_BASE_ADR + BB_TX_BUFFER_SIGNAL + 1, to address value, TX_BASE_ADDRESS + BB_TX_BUFFER_SIZE.

Transmission of data continues until PSDU_LENGTH[10:0] bytes are sent, the INTERRUPT_TX_EOF interrupt goes high if enabled, or the user issues the CMD_PHY_ON_15d4 command.

Rolling Buffer in Receive Mode

In receive mode, the RX_BASE_ADDRESS register sets the start of the rolling buffer in packet RAM. The BB_RX_BUFFER_ SIZE register sets the size of the buffer. Do not allow the buffer size to exceed the available packet RAM. When the value in the BB_RX_BUFFER_SIZE register is added to the value in the RX_BASE_ADR register, do not exceed 0x0FF. If the 16-bit FCS checking on the ADF7023-J is enabled, 0x0FD is not exceeded.

Set the value in the BB_RX_BUFFER_SIGNAL register so that an INTERRUPT_BUFFER_ALMOST_FULL interrupt is asserted prior to the buffer being filled by received data. Typically, the BB_RX_BUFFER_SIGNAL register is set so the interrupt is asserted when half the buffer has been filled with received data.

When an INTERRUPT_BUFFER_ALMOST_FULL interrupt is asserted, the host microprocessor reads in the data in the locations from address value RX_BASE_ADDRESS to address value, RX_BASE_ADR + BB_RX_BUFFER_SIGNAL.

When the last byte of the Rx buffer has been filled, the ADF7023-J continues writing the received data starting at the RX_BASE_ADR register. If enabled, an INTERRUPT_BUFFER_ FULL interrupt is asserted when the buffer has been filled.

When an INTERRUPT_BUFFER_FULL interrupt is asserted, the host microprocessor reads in the data in the locations from address value, RX_BASE_ADDRESS + BB_RX_BUFFER_SIGNAL + 1, to address value, RX_BASE_ADDRESS + BB_RX_BUFFER_SIZE.

Reception of data continues until the number of bytes defined in the PSDU_LENGTH[10:0] word has been received and INTERRUPT_RX_EOF and/or INTERRUPT_CRC_CORRECT are asserted (if enabled), or the host microprocessor issues the CMD_PHY_ON_15d4 command.

Note that if a 16-bit CRC is enabled (16-bit FCS), the FCS bytes are placed into the packet RAM as two bytes after the payload, outside of the rolling buffer control. What this means is that if the payload fills up to address value, RX_BASE_ADDRESS + BB_RX_BUFFER_SIZE, when the 16-bit FCS is calculated and checked vs. the incoming FCS, the received FCS bytes are placed in the next two memory locations (beyond the address value, RX_BASE_ADDRESS + BB_RX_BUFFER_SIZE). If another buffer is defined to start in the memory location immediately following an address value, RX_BASE_ADDRESS + BB_RX_BUFFER_SIZE, in this instance the first two bytes are overwritten.

To avoid this situation arising for any length and buffer size, leave an overflow area of two bytes vacant immediately after the Rx buffer. If the Rx buffer is assigned to the upper part of the packet memory, set it to not exceed memory location 0xFD.

If the Rx buffer is placed lower down in packet memory, and is immediately followed in packet memory by a Tx buffer, set the TX_BASE_ADR register to be three bytes greater than address value, RX_BASE_ADDRESS + BB_RX_BUFFER_SIZE. This procedure ensures that if the payload length places the packet end at the BB_RX_BUFFER_SIZE boundary, the overflow of the FCS bytes does not cause overwriting of the first two bytes of the following Tx buffer. The FCS bytes are written into the overflow bytes, instead.

This overwriting issue does not arise in 32-bit CRC mode. In 32-bit CRC mode, the ADF7023-J does not calculate the CRC itself, so the incoming four bytes of FCS are considered the same as the payload, and are loaded into the receive buffer under rolling buffer control.

Recommended Register Settings

Recommended Automatic Gain Control (AGC) Settings

To optimize the receiver for robust PER performance over the full input power range, overwrite the default AGC clock divide setting in the modem configuration random access memory (MCR). It is recommended to set the AGC_CLOCK_DIVIDE register (Address 0x32F) to 0x12.

Tx Lookup Table (LUT) Settings

The optimized phase-locked loop (PLL) bandwidth settings for T108 operation are built into the AD_15d4g firmware download. Therefore, it is unnecessary to write a custom transmit LUT. Set Bits[5:4] of the RADIO_CFG_7 register (Address 0x113) to 0 when using the PHY_TX_15d4 state.

Reused BBRAM Settings

The ADF7023-J AD_15d4g firmware download reuses the BBRAM registers, and, thus, some default functions are no longer available when in 15d4 mode (see Table 1).

Smart wake mode is not available with the AD_15d4g firmware download because BBRAM Address 0x103, Address 0x104, and Address 0x105 are reused for CCA functionality in the firmware download.

Address matching and static register fix are not available with the AD_15d4g download because BBRAM Address 0x129 to Address 0x137 are reused by the firmware to control the antenna diversity and packet structure.

Transmit test modes are not available within the PHY_TX_ 15d4 state. To use the transmit test modes, it is necessary to revert to the PHY_ON state to get to the PHY_TX state.

To use the optimized PLL settings for T108 operation in PHY_TX state, the sequence outlined in the ADF7023-J data sheet must be followed.

Therefore, the full sequence from the PHY_ON_15d4 state to transmit test mode with optimized T108 PLL settings is as follows:

1. Issue Command 0xB1 to exit 15d4 mode.
2. Use the custom transmit LUT. Write 0x2 to Bits[5:4] of the RADIO_CFG_7 register (Address 0x113).
3. Issue the CMD_CONFIG_DEV command.
4. Write the custom LUT, as defined in Table 36.
5. Select the transmit test mode desired (see the test modes information in the ADF7023-J data sheet).
6. Enter the PHY_TX state.

Example Receiver Settings for 100 kbps and 200 kbps Operation, Automatic Frequency Control (AFC) Enabled

Specifications

All specifications are for 100 kbps, 50 kHz deviation only unless otherwise indicated.

Test Conditions

Code Download Sequence

The AD_15d4g firmware download module must be stored in the PRAM starting from Address 0x0000.

The program RAM can be written to only by using the memory block write. Set the SPI_MEM_WR command to 0x1E.

The sequence to write a firmware module to program RAM is as follows:

1. Ensure that the ADF7023-J is in the PHY_OFF state.
2. Issue the CMD_RAM_LOAD_INIT command.
3. Write the module to PRAM using an SPI memory block write.
4. Issue the CMD_RAM_LOAD_DONE command.

The firmware module is now stored on program RAM.

著者

Liam O'Hora