Doc ID: DOC-1708

Change

In Table 4-11, the Peripheral column is incorrect for the 63, 64, and 65 entries in the Write-Protect Register and Secure Peripheral Number (n) column. The correct peripherals for these entries are:

Write Protect Register and Secure Peripheral Number 63 is USB0

Write Protect Register and Secure Peripheral Number 64 is RTC0

Write Protect Register and Secure Peripheral Number 65 is PKTE0

Doc ID: DOC-1746

Change

Step 6 in the System Interrupt Flow procedure is incorrect.

Current:

The SEC compares the SEC_CPND[n](B) register value to the SEC_CACT[n](A) register value. If the SEC_CACT[n] (A) register value is a higher priority, continue.

Change to:

The SEC compares the SEC_CPND[n](B) register value to the SEC_CACT[n](A) register value. If the SEC_CPND[n](B) register value is a higher priority, continue.

Doc ID: DOC-1759

Change

Table 13-1: ADSP-BF70x OTP Layout shows the wrong bootModeDisable byte address and incorrect fsn entry.

INCORRECT: Byte Address for bootModeDisable is 0x30 = 24 - 0x343.

CORRECT: Byte Address for bootModeDisable is 0x340 = 24 - 0x343.

Remove table row for fsn

Doc ID: DOC-1966

Change

The Hash Module topic includes info that is not correct. The last sentence does not apply to the hash module on this processor.

A second AESCBC module for the hash function enables parallel processing for AES-CCM, a combined hash and encrypt algorithm.

Doc ID: DOC-1777

Change

The TWI0 Voltage Select field (PADS_PCFG0.TWI0VSEL) is incorrect.

The correct enumeration is:

0 – VDD_EXT = 3.3V, VBUS_TWI = 3.3V

1 – VDD_EXT = 1.8V, VBUS_TWI = 1.8V

2 – Reserved

3 – VDD_EXT = 1.8V, VBUS_TWI = 3.3V

4 – VDD_EXT = 3.3V, VBUS_TWI = 5.0V

5-7 – Reserved

Doc ID: DOC-1834

Change

Table 21-36 shows the incorrect mode for the TINSEL (Timer Input Select) bit description.

INCORRECT: Timer Input Select (for WIDCAP, WATCHDOG, PININT modes).

CORRECT: Timer Input Select (for WIDCAP, EXTCLK, PININT modes).

Doc ID: DOC-1840

Change

Table 26-15 shows an incorrect BUFRDERR (Buffer Read Error) bit description.

INCORRECT: The TWI_MSTRSTAT.BUFRDERR indicates whether the current master transfer was aborted due to the detection of a NAK during data transmission. This bit is W1C.

0 No Status

1 Buffer Read Error

CORRECT: The TWI_MSTRSTAT.BUFRDERR indicates whether the current master transfer was aborted due to a buffer read error.

0 The current master transmit has not detected a buffer read error

1 The current master transfer was aborted due to a transmit buffer read error. At the time data was required by the transmit shift register the buffer was empty. This bit is cleared by writing a one to its bit location.

Last Update Date: 2025年01月08日