Does Analog Devices offer a list of manufacturers of oscillators for DDS devices?

We do not recommend a specific manufacturer, but Ecliptek, Epson, Vari-L, Connor-Winfield, Wenzel, and Valpey-Fisher are known as sources for high quality parts.

Why can't I see a signal at the output of my DDS when it is unterminated? (I'm setting everything correctly, but I'm just probing the output pins of the DDS which have nothing connected to them.)

All ADI DDS ICs have DACs with current-mode outputs. It is necessary to convert the current to a voltage by passing the output through an appropriate value of resistor before a voltage signal can be measured. Also, a balanced-to-balanced, or balanced-to-unbalanced transformer may be used. The transformer must be center-tapped on the DDS side in order to provide a current path for the DAC outputs.

The output from the DDS DAC is a pair of complementary currents, set by the external Iset resistor to a suitable value. This current is usually 10mA, or sometimes 20mA. This is a fixed current, which is steered between the Iout and Iout_bar DAC output pins according to the digital code applied to the DAC at the instant. Full scale positive results in all of the current coming out of the Iout pin, and none out of the Iout_bar pin. Full scale negative is the opposite – all of the current coming out of the Iout_bar pin, none out of the Iout pin. Midscale on the DAC results in equal amounts of current coming from both pins simultaneously. The sum of the currents at any instant is always equal to the Iset current.

The fact that the DDS outputs are current sources means that the outputs must always have a current path to ground (or VCC in some DDSs). The current sources have a voltage compliance of only about 1V. This means that when Iset is 20mA, the maximum resistive load is 50 ohms. The need for a current path also explains why a center-tapped transformer is usually used when a balanced output is desired.

Note: The AD9852 and AD9854 also have an output scale factor multiplier which defaults to 0000. This will also prevent you from seeing any output signal until the scale factor is bypassed or set to some non-zero value.

Where can I find some good background material on direct digital synthesis?

The following DDS tutorials should be helpful: A Technical Tutorial on Digital Signal Synthesis and
Tutorial MT-085, Fundamentals of Direct Digital Synthesis

クロックが変わった場合の位相シフトの分解能

Q：   可変位相シフト・レジスタが内蔵されたＤＤＳでは、マスタークロックが変わった場合、設定できる最小分解能のステックは変わるのでしょうか。

A：   位相シフトの設定は、マスタークロック（Ｒｅference Clock）の周波数には依存しません。たとえば12ビット分解能のレジスタであれば、分解能は、360 / 4096≒0.088°です。