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Results on EngineerZone

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    1. Best Practice for MCLK and Audio Clocking: External Crystal vs MCU-Generated MCLK, Codec vs MCU BCLK/LRCLK Generation

      Forum Thread
      Answered
      ADSP-SC59x
      29 April, 2025
      Hi, I'm currently designing a system based on an MCU and an Analog Devices ADSP-21573 DSP, connected via I²S/TDM to an external audio codec. I have a few questions regarding the optimal audio clock architecture to ensure best sound quality (lowest jitter, highest stability): MCLK generation: Should …
      Audio Signal Processorsbclksoftwaresample rateadsp-21573mclkcodecSHARC Audio Processors/SoCsaudio

    2. Using ASRC and not getting audio output from analogue connector

      Forum Thread
      Answered
      SigmaDSP Processors & SigmaStudio Dev. Tool
      28 April, 2025
      … EVAL-ADAU1452 board, and whilst I see decent metering and control of sources on the incoming TDM8 bus, I can't seem to then get audio from ASRC -> DSP -> Serial Output 0 (headphone output on eval board). In my file I have a little white noise source that I switch …
      Audio Signal Processorsadau1452hardwareadau1452 sigmastudioasrc tdmSigmaDSP Audio Processors

    3. ADF4159 AUX

      Forum Thread
      Answered
      RF and Microwave
      20 April, 2025
      If I use the ADF5901 or another chip along with the ADF4159 to generate a chirp signal, I know that if I connect AUX and AUXB to RFINA and RFINB, a differential 100-ohm microstrip line is required. Would it be possible to connect only one of these paths? For …
      hardwareMicrowave and mmWave TransmittersRF Integrated TransmittersFractional-N PLLadf4159Phase Locked Loop (PLL) Synthesizer &amp; Translation Looprf and microwave

    4. Is AD7794 Auto cycling?

      Forum Thread
      Answered
      Precision ADCs
      16 April, 2025
      Hey you... I wonder if AD7794 in continuous conversion and read mode is auto cycling between channels or not? and if yes how to configure it? thanks in advance for your guidance
      Datasheet/SpecsMultiplexed A/D Convertersad7794AD7794 #ADCsPrecision A/D Converters

    5. Audible noise issue

      Forum Thread
      Answered
      SigmaDSP Processors & SigmaStudio Dev. Tool
      13 April, 2025
      My customer said that audible noise occurred during development in the environment below. Is it because of the mismatch in sampling frequency of I2S input and output? They want it to work normally when the input frequency is 44.1kHz, 48kHz. Is it possible to change the I2S input frequency …
      Audio Signal ProcessorsDatasheet/Specsadau1467SigmaDSP Audio Processors

    6. Audio Codec MAX98091 EVK || Evaluation software issue

      Forum Thread
      Answered
      Speech Processing Solutions
      04 April, 2025
      Hello Team, We are doing bring up of Audio Codec Max98091 with NXP I.MX8M Plus but before that we need to validate Evalution board with Max98091 Evaluation software, but it is showing compatibility only till Windows 8. As we don't have windows 8 PC and we need to …
      Integrated/Special Purpose A/D ConvertersMaximaudio codecAudio CODECs

    7. Can this be used for audio routing?

      Forum Thread
      Answered
      Switches/Multiplexers
      25 March, 2025
      I would like to create a system to patch any one of 160 inputs in a modular synthesizer system to any one of 160 outputs. My understanding is that using a 16x16 crosspoint switch IC would require 100 chips, so the 32x32 would only need 25, correct?
      hardwareswitches and multiplexersBuffered Analog Crosspoint Switchesadv3200audio

    8. Automated TDD in TES - clocking

      Forum Thread
      Answered
      Design Support ADRV9001 – ADRV9007
      20 March, 2025
      I'm using TES to develop a customised automated TDD profile. The user guide states that all enablement timings are relative to a 'system clock' frequency of 184.32 MHz. In my application I have the Tx/Rx sample rate set to 48 MHz. Within the TDD Enablement Delays tab …
      teshardwareADRV9002tddWideband Transceiver ICRF Integrated Transceivers

    9. ADV7619 Audio LRCLK jitter

      Forum Thread
      Answered
      Video
      24 February, 2025
      HI, I would like to know the maximum jitter I should expect on the LRCLK output of the ADV7619 if the HDMI source is compliant with the spec? I guess the internal audio PLL as non negligeable impact on audio jitter. Thanks, Denis Alain, Eng.
      Datasheet/Specsaudio_pathclock and timingHDMI/DVI ReceiversHDMI/DVI Devicesadv7619

    10. AuxADC filtering

      Forum Thread
      Answered
      Design Support AD9361/AD9363/AD9364
      11 February, 2025
      Good Morning. Into Reference Manual, it is advise to add a small value capacitor (680pF) on AuxADC pin. As I'm reading temperature sensor (static measure), I'd like to add an higher capacitor value (1uF) for filtering. Does AD9361S impose any recommendation for higher value ? Thanks per advance. Sincerely …
      hardwareAD9361S-CSHfilterauxadcAD9361SWideband Transceiver ICRF Integrated Transceivers