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  1. AD7891
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    Multiplexed A/D Converters
    True Bipolar Input, Single Supply, Parallel, 8-Channel, 12-Bit High Speed Data Acquisition System
    AD7891

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Results on EngineerZone

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    1. petalinux 2021.2 driver for ad9361

      Forum Thread
      Answered
      Linux Software Drivers
      10 April, 2025
      … board with xc7z045 and ad9361 on board. I am using bare metal application downloaded from adi site "hdl-2021_R2" with some modification in hdl-2019_r1\projects\adrv9361z7035\ccbob_lvds project I am able to run baremetal application. Now I want to add ad9361 drivers in petalinux2021.2. I …
      softwarePetaLinux2021.2ad9361Wideband Transceiver ICRF Integrated Transceivers

    2. LTSpice Simulations with ADA4807-2 device (.cir model and LTSpice circuit) not aligned with actual circuit measurements

      Forum Thread
      Answered
      Operational Amplifiers
      10 April, 2025
      Hello, I have a full-wave rectifier circuit (without diodes) circuit based on ADA4807-2 device and measurements do not match with LTspice simulations. I tried the ADA4807-2 IC included in the LTspice library and also the ADA4807-2.cir model available on the web as well. Both showed …
      Operational Amplifiers (Op Amps)amplifiersspice modelhardwareLTspiceHigh Speed Op Amps (Bandwidth = 50MHz)ada4807-2

    3. Regarding ADA4896 Fig. 29

      Forum Thread
      Answered
      Operational Amplifiers
      09 April, 2025
      The datasheet's Fig. 29 shows the waveform of the recovery time when the input is overdriven. When the input conditions are VS = 5V, G = 1, the input range of this IC is 0.1V to 4.1V according to the table specifications. However, the horizontal axis (INPUT) of Fig …
      Operational Amplifiers (Op Amps)Datasheet/SpecsLow Noise Op Amps (= 10nV/vHz)ada4896-2

    4. CCES 2.12.1 Installation failed with bluescreen

      Forum Thread
      Answered
      CrossCore Embedded Studio and Add-ins
      08 April, 2025
      Hi all, I just downloaded the 2.12.1 version of CCES, installed it on a brand-new Lenovo P16s and during driver installation (the third or fourth one), I got a bluescreen. I started Windows again and saw that the installation was not complete, i.e. I could neither …
      softwareinstallationproblemCCES 2.12.12.12.1

    5. Inquiry About External Capacitor on HMC435 RF Switch (Pins 1, 2 - A, B)

      Forum Thread
      Answered
      RF and Microwave
      07 April, 2025
      I am currently reviewing the datasheet for the HMC435 RF switch and I have a question regarding pins 1 and 2 (A and B). In the simplified schematic provided in the datasheet, it shows that a capacitor is connected in parallel with these control pins. However, I could not find …
      Datasheet/SpecsSP8TspdtspstSP6TSP5Tsp4tRF SwitchesSP3Thmc435a

    6. Invalid raw value while trying to read feed 4-20 current input to EVK ADS4111 kit

      Forum Thread
      Answered
      Precision ADCs
      01 April, 2025
      … EN, 2 }, { AD717X_ID_REG, , 2 }, { AD717X_CHMAP0_REG, , 2 }, { AD717X_CHMAP1_REG, , 2 }, { AD717X_CHMAP2_REG, , 2 }, { AD717X_CHMAP3_REG, , 2 }, { AD717X_CHMAP4_REG, , 2 }, { AD717X_CHMAP5_REG, , 2 }, { AD717X_CHMAP6_REG, , 2 }, { AD717X_CHMAP7_REG, , 2 }, { AD717X_CHMAP8_REG, , 2 }, { AD717X_CHMAP9_REG, , 2 }, { AD717X_CHMAP10_REG, , 2 …
      softwareMultiplexed A/D ConvertersADS4111Precision A/D Converters

    7. I Could not receive synchronized DAC output from 2 ad9959 eval board

      Forum Thread
      Answered
      Direct Digital Synthesis (DDS)
      27 March, 2025
      I want to generate synchronized 8-channel signals using two AD9959 evaluation boards. For this, I am using a synchronized 50 MHz REFCLK. When I check the SYNC_CLK pins of the boards on an oscilloscope, the clock signals appear to be synchronized. Without making any adjustments in the evaluation …
      hardwareclock and timingad9959ddsDirect Digital Synthesis (DDS)

    8. axi-ad9162-hpc "attr 2: scale ERROR: Invalid argument"

      Forum Thread
      Answered
      FPGA Reference Designs
      18 March, 2025
      … i: (output, index: 0, format: le:S16/16>>0)3 channel-specific attributes found:attr 0: fir85_enable value: 0attr 1: sampling_frequency value: 1966080000attr 2: scale ERROR: Invalid argument (22)voltage0_q: (output, index: 1, format: le:S16/16>>0)3 channel-specific attributes found:attr 0: fir85_enable …
      software0431845-10-2318libiiopython 3.10

    9. JESD 204C 64b66b Link Receive Layer

      Forum Thread
      Answered
      FPGA Reference Designs
      12 March, 2025
      … 1 According to the formula E*32*8 -1 (taken from above formula) I'm setting OCTETS_PER_MULTIFRAME = TPL_BEATS_PER_MULTIFRAME = F parameter = 2 OCTETS_PER_FRAME = Others CSR configs are default values The links aren't coming up. Can anyone help bring clarity to these registers: (a …
      Datasheet/SpecsAD9081rtlJesd FrameworkHigh Speed A/D Converters &gt;10 MSPSjesd204cMixed-Signal Front Ends (MxFE)receive

    10. ADF4110/1/2/3 reference input sensitivity - why is it 3.0Vpp min @AV DD = 5 V, while it is 0.4Vpp min at 3.3V? Why so extremely different?

      Forum Thread
      Answered
      RF and Microwave
      10 March, 2025
      https://ez.analog.com/rf/f/q-a/165134/adf4113-convert-v-to-dbm also indicates that the sensitivity is similar, is 3.0V really correct? Regards, Alexander
      Datasheet/Specs