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  1. DAC10
    Not Recommended for New Designs
    Product
    Multiplying Current Output D/A Converters
    10-Bit High Speed Multiplying D/A Converter (Universal Digital Logic Interface)
    DAC10

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    Sample & Buy

  2. DAC100S
    Production
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    Multiplying Current Output D/A Converters
    Aerospace 10-Bit Current Output DAC
    DAC100S

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    Sample & Buy

  3. DAC10Z/MDA10Z: Low Cost General Purpose Digital to Analog Converter Obsolete data Sheet
    Obsolete Data Sheet

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    762 kB

  4. DAC100S: 10-Bit Current Output D to A Converter Aerospace Data Sheet
    Data Sheet

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    173 kB

  5. DAC10ZMDA10Z
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    DAC10ZMDA10Z

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  6. AD9910: 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer Data Sheet
    Data Sheet
    The AD9910 is a direct digital synthesizer (DDS) featuring an integrated 14-bit DAC and supporting sample rates up to 1 GSPS.

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    1.21 M

  7. DAC16: 16-Bit High Speed Current-Output DAC Obsolete Data Sheet
    Obsolete Data Sheet

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    190 kB

  8. DAC10: 10-Bit Current-Out DAC Data Sheet
    Data Sheet

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Results on EngineerZone

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    1. FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

      Forum Thread
      Answered
      FPGA Reference Designs
      02 January, 2018
      Hello friends, happy new year to all of you, I hope this year goes all well and happy for you and your family. I come to my question, as I mentionned on old posts, I 'm working on FMCDAQ2 and xilinx carrier KC705, I'm using the version 2017_R1 …
      ad9680High Speed A/D Converters &gt;10 MSPSStandard High Speed A/D Converters

    2. RE: FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

      Forum Reply
      FPGA Reference Designs
      09 January, 2018
      hi Umesh, I do another post to clarify my question under the title : FMCDA2 USING DACPLL

    3. RE: FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

      Forum Reply
      FPGA Reference Designs
      09 January, 2018
      Hi Umesh, I did a change using the DACPLL, now DACCLK=1.2Ghz (before it was 600Mhz), of course the JESD204B will not work as before and the AD9144_setup gives PLL not locked, I thought that won't affect the RX path, when I capture the RX data, I …

    4. RE: FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

      Forum Reply
      FPGA Reference Designs
      08 January, 2018
      Hi Umesh, I have another Idea to solve my problem, I think it could easy to implement: My starting Point: the configuration DAC @ 600Mhz and ADC 300Mhz is working fine My constraints: is to have data on RX path at max 300Mhz My Objective: is to increase the DAC sampling …

    5. RE: FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

      Forum Reply
      FPGA Reference Designs
      07 January, 2018
      Thank you very much Umesh, I will work on your suggetions, I hope I will progress with these informations you provided me, I will let you know, again many thanks to you (please forget my last post VCO of the PLL at 3.6Ghz, it's not possible, since the …

    6. RE: FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

      Forum Reply
      FPGA Reference Designs
      06 January, 2018
      Hello, I think i mis-spoke. I apologize for that. "Can you please try L=2, M = 2, F = 2? = 49h; = 10h, or L = 1, M = 2, F = 4; = 0Ah; = 00h?" I am not an FPGA expert, so unfortunately I will not be of much use there. For L.M …

    7. RE: FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

      Forum Reply
      FPGA Reference Designs
      06 January, 2018
      Hello Umesh, Another alternative may be easier, is how can I set the VCO of the PLL at 3.6Ghz instead of 3.0 Ghz, This will allow to put the DAC at 1.2 Ghz instead of 1Ghz and set the ADC @ 300Mhz instead of make a decimation by …

    8. RE: FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

      Forum Reply
      FPGA Reference Designs
      04 January, 2018
      hello Umesh, when I used this = 0Ah; = 10h and set lane_rate_kbs = 10000000 or this = 49h; = 10h and set lane_rate_kbs = 5000000 the PLL locks I don't get the message PLL not Locked. My question how can I adapt all other parameters (in bold), what can I …

    9. RE: FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

      Forum Reply
      FPGA Reference Designs
      04 January, 2018
      Hi, Under the conditions you have listed (L=4; M = 2; F = 1), the line rate calculated would be (M x N' x (10/8) x Fout) / L = (2 x 16 x (10/8) x (1000M/4)) / 4 = 2.5Gbps. This falls below the supported lane rate of the AD9680 …

    10. RE: FMCDAQ2 ADC Decimation in mode ADC1Ghz-DAC1Ghz

      Forum Reply
      FPGA Reference Designs
      03 January, 2018
      Hi Umesh Thanks for your feedback, in register (QUICK_CONFIG) = and regsiter (LANE_RATE_CTRL) = if lane_rate_kbs 6250000