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Analog Devices Inc. logo Results on Analog.com
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    1. AD9852
      Production
      Product
      Direct Digital Synthesis (DDS)
      CMOS 300 MSPS Complete DDS
      AD9852

      PDF

      Datasheet

      Documentation

      Ask the Community

      Sample & Buy

      Sample & Buy

    2. Why did the model numbers change on the AD9852 and AD9854 products? I thought they were available in the ASQ package.
      Frequently Asked Question
      … new SV-80 package types are pin for pin compatible with the footprint of the SQ-80. The data sheet will change to REQUIRE the exposed paddle on the SV-80 package be soldered to the circuit board for thermal reasons. The SV-80 package is slightly thinner (1.00 vs 1.40 nominal). The exposed paddle is square rather than octagonal, but roughly the same size. The AD9852AST and AD9854AST packages are still available.
    3. AD9852: CMOS 300 MSPS Complete DDS Data Sheet
      Data Sheet

      PDF

      AD9852: CMOS 300 MSPS Complete DDS Data Sheet

      1375 kB

    4. AD9857
      Production
      Product
      Quadrature Digital Up Converters (QDUC)
      CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
      AD9857

      PDF

      Datasheet

      Documentation

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      Sample & Buy

    5. AD9856
      Production
      Product
      Quadrature Digital Up Converters (QDUC)
      CMOS 200 MHz Quadrature Digital Upconverter
      AD9856

      PDF

      Datasheet

      Documentation

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      Sample & Buy

    6. AD9854
      Production
      Product
      Direct Digital Synthesis (DDS)
      CMOS 300 MSPS Quadrature Complete DDS
      AD9854

      PDF

      Datasheet

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      Sample & Buy

    7. AD9854/AD9852 Evaluation Board Instructions
      Evaluation Design File

      PDF

      AD9854/AD9852 Evaluation Board Instructions

      29.96 K

    8. AD8452
      Recommended for new designs
      Product
      Industrial Battery Manufacturing
      Precision Integrated Analog Front End, Controller, and PWM for Battery Test and Formation Systems
      AD8452

      PDF

      Datasheet

      Documentation

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      Sample & Buy

    9. AD9753
      Production
      Product
      Standard High Speed D/A Converters
      12-Bit, 300 MSPS High Speed TxDAC+® D/A Converter
      AD9753

      PDF

      Datasheet

      Documentation

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      Sample & Buy

    10. AD9751
      Production
      Product
      Standard High Speed D/A Converters
      10-Bit, 300 MSPS High Speed TxDAC+® D/A Converter
      AD9751

      PDF

      Datasheet

      Documentation

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    Results on EngineerZone

    27
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      1. MSL and CSD-HBM information

        Forum Thread
        Answered
        RF and Microwave
        21 March, 2025
        … ADUM1311ARWZ-RL LTC5507ES6#PBF ADL5331ACPZ-WP AD8319ACPZ-R2 AD8310ARMZ LT3439EFE#PBF AD8230YRZ-REEL LTC1151CSW#PBF LT1991ACMS#PBF LM399AH#PBF LT1962EMS8#PBF LTC2418CGN#PBF AD8276ARZ-R7 AD9852ASTZ AD8041ARZ ADR292GR LT1129IS8-5#PBF TMP01ESZ AD9220ARSZ AD7476ARTZ-500RL7 AD7812YR-REEL ADUM1201BRZ-RL7 ADUM1412BRWZ-RL LTC1444IS#TRPBF LTC1728HS5-5#PBF LT1376IS8-5#PBF LTC4211IMS …
        Datasheet/SpecsDigital Isolation TechnologyStandard Digital IsolatorsADUM160N

      2. AD9852ASVZ - No internal update clock generated

        Forum Thread
        Answered
        Direct Digital Synthesis (DDS)
        18 July, 2013
        I'm new to using AD9852 and have difficulty starting it up. In conclusion, there seems to be no internal update clock generated upon POR. According to the datasheet, the update clock mode is internal upon POR. Therefore, if the reference clock is normally fed into the device, the internal …
        clock and timingad9852Direct Digital Synthesis (DDS)

      3. AD9852ASQ replaced with AD9852ASVZ

        Forum Thread
        Answered
        Direct Digital Synthesis (DDS)
        08 September, 2011
        I am having a temperature problem. Both parts have the ground paddle that are being solder down. However, ASVZ is going unlocked when cca is at 64 C. Both parts are rated to 85 C. Has anyone noticed temperature problem with ASVZ? I am not seeing problem with ASQ. I …

      4. Vs Current ( or Pdss) of AD9854ASTZ

        Forum Thread
        Answered
        Direct Digital Synthesis (DDS)
        27 March, 2025
        If looking at page 7 of datasheet(Rev.F) The following three types of numbers s are specified in Power Supply. What does this mean? Vs Current 865mA (MAX) , 585mA (MAX) & 495mA (MAX) Toru
        hardwareclock and timingad9854Direct Digital Synthesis (DDS)

      5. RE: Vs Current ( or Pdss) of AD9854ASTZ

        Forum Reply
        Direct Digital Synthesis (DDS)
        01 April, 2025
        Jules.Nikko said:Jules Hi Jules, I understood. Thank you for your kind assistant Toru

      6. RE: AD9852ASQ replaced with AD9852ASVZ

        Forum Reply
        Direct Digital Synthesis (DDS)
        29 April, 2019
        This question has been closed by the EZ team and is assumed answered.

      7. RE: AD9852ASVZ - No internal update clock generated

        Forum Reply
        Direct Digital Synthesis (DDS)
        02 August, 2018
        This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.Thank you,EZ Admin

      8. RE: AD9852ASVZ - No internal update clock generated

        Forum Reply
        Direct Digital Synthesis (DDS)
        25 July, 2013
        Note, the default register value in parallel register 19h in the AD9852 data sheet (page 32) should be 40h or 64decimal, and not 00h.. This means you should get a IO_UPDATE pulsing at the appropriate rate after the master reset. I remmebering hearing if the unused DAC output s …

      9. RE: AD9852ASVZ - No internal update clock generated

        Forum Reply
        Direct Digital Synthesis (DDS)
        21 July, 2013
        Hi, Have you programmed the 32-bit update clock register (Address 16hex to Address 19hex)? That is because, even if the default value of internal/external update clock register bit is logic high, you still need to set the update rate. Note, the default value of the 32-bit register …

      10. RE: AD9852ASVZ - No internal update clock generated

        Forum Reply
        Direct Digital Synthesis (DDS)
        18 July, 2013
        UPDCLK behaves strange in the figure below. It operates just for several cycles after POR and stops. Moreover, the period of each pulse signal is not the same as one another.

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