Magnifying Glass Icon close icon

You searched for “AD9054BST-135”

Filters

Filter Icon

Filters

Expand or Collapse Filter Icon
Expand or Collapse Filter Icon
Resources
Expand or Collapse Filter Icon
Site Section
  • 1
Expand or Collapse Filter Icon
Result Type
  • 7
  • 134
  • 1,927
  • 482
  • 7
  • 1
Expand or Collapse Filter Icon
Groups, Forums & Libraries
  • 29
  • 22
  • 88
  • 17
  • 79
  • 85
  • 234
  • 91
Expand or Collapse Filter Icon
Author
  • 10
  • 373
  • 17
  • 13
  • 13
  • 18
  • 28
  • 19
Expand or Collapse Filter Icon
Tag
  • 128
  • 75
  • 64
  • 62
  • 53
  • 51
  • 50
  • 50

Results on Analog.com

1
Relevance

Sort by

External Link Icon Right Arrow Icon External Link Icon External Link Icon Tag
  1. AD9054A: 8-Bit, 200 MSPS A/D Converter Data Sheet
    Data Sheet

    PDF

    330 kB

  • <<
  • <
  • 1
  • >
  • >>

Results on EngineerZone

2,558
    Clear All Filters Icon

    1. How is source clock phase noise profile related to observed phase noise in AD6676 (datasheet fig. 135)?

      Forum Thread
      Answered
      High-Speed ADCs
      18 January, 2019
      … be to just use the HMC7044. However, it's not clear to me how the clock source phase noise relates to the results in figure 135 of the datasheet. I assume that what figure 135 is depicting is the phase noise you would see on your screen if you injected …
      Clock Generation DevicesClock Generation and Distributionhmc7044ad6676clock and timingphase noiseHigh Speed A/D Converters &gt;10 MSPSIF/RF Receivers

    2. How we can TX band detected sample between 135 MHz and 175 MHz using adrv9361-Z7035?

      Forum Thread
      Answered
      Design Support AD9361/AD9363/AD9364
      21 October, 2018
      Hi, Prestigious Guiders i need your help for solving the problem which is: I am using adrv9361-z7035 transceiver and FMCOMMS3,i want to know how transmission can be done between 135 MHz to 175 MHz band using this hardware.Provide me any documentation of complete procedure a to z …

    3. RE: How is source clock phase noise profile related to observed phase noise in AD6676 (datasheet fig. 135)?

      Forum Reply
      High-Speed ADCs
      07 February, 2019
      Hello David, Data presented in figure 135 used the R&S SMA100A (with low phase noise option) for the signal source as well as clock source (either as reference to PLL or Direct RF clock input. We did not characterize the SMA100A with phase noise analyzer albeit phase noise plots …

    4. RE: How we can TX band detected sample between 135 MHz and 175 MHz using adrv9361-Z7035?

      Forum Reply
      Design Support AD9361/AD9363/AD9364
      29 October, 2018
      Please refer https://wiki.analog.com/resources/eval/user-guides/adrv936x_rfsom/user-guide/introduction https://wiki.analog.com/resources/eval/user-guides/adrv936x_rfsom/user-guide/software

    5. ADF 5355 VCO Readback Waveform incorrect in AN-1353 Figure 2 VCO Readback?

      Forum Thread
      Answered
      RF and Microwave
      23 July, 2023
      … seem to get the correct core and band values when I ignore first 2 bits instead of only first bit (Figure 2. VCO Readback AN-1353)Does the bias code readback have the same problem or is Figure 2. VCO Readback AN-1353 correct for the bias code? This is …
      hardwareFractional-N PLLPhase Locked Loop (PLL) Synthesizer &amp; Translation Looprf and microwaveadf5355

    6. ACEInstall_1.21.3003.1356

      Forum Thread
      Answered
      Analysis Control Evaluation (ACE) Software
      04 April, 2021
      The installation link to the ACE software is broken. It returns File Not Found.

    7. BROKEN LINK: ACE Installer Software 1.21.3003.1356

      Forum Thread
      Answered
      Analysis Control Evaluation (ACE) Software
      04 April, 2021
      The ACE installation link is broken: https://swdownloads.analog.com/ACE/ACEInstall_1.21.3003.1356.exe

    8. Sigma Studio Ver 3.11 Build 1. Rev 1356 Mixer Bug?

      Forum Thread
      Answered
      SigmaDSP Processors & SigmaStudio Dev. Tool
      21 August, 2014
      I'm running Sigma Studio Ver 3.11 BUild 1. Rev 1356. And I have a 4 input, 3 output mixer. My assumption from reading the literature is that the inputs are represented by the rows of controls, while the outputs are the columns creating a 4-row, 3 …

    9. ADV7441: HD with 1350 total lines don't work on DVI

      Forum Thread
      Answered
      Video
      07 August, 2013
      HD with 1350 total lines don't work on DVI.
      Video ProductsVideo Decodersadv7441

    10. When using the MAX17502G with a negative output configuration as outlined in APP5775 is the EN/UVLO still 1.218V (nominal) to enable 1.135V (nominal) to disable?

      Docs & FAQs
      Power Management
      Yes in the configuration given in App Note 5775 the EN/UVLO voltages are still 1.218V (nominal) to enable, and 1.135V (nominal) to disable. However, the manner in which the circuit is set up in this configuration means that once powered up, in order for the chip …
      Negative OutputMAX17502GKA-01181AN5775MAX17502GATB+