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  1. AD5248
    Production
    Product
    Digital Potentiometers (DigiPOT)
    256-Position Dual Channel I2C Compatible Digital Resistor
    AD5248

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    Sample & Buy

    Sample & Buy

  2. AD5243
    Production
    Product
    Digital Potentiometers (DigiPOT)
    256-Position Dual Channel I2C Compatible Digital Potentiometer
    AD5243

    PDF

    Datasheet

    Documentation

    Ask the Community

    Sample & Buy

    Sample & Buy

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Results on EngineerZone

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    1. ADRV9002 Frequency Hopping Mode Causes 5 dB TX Power Drop (Linux Drivers)

      Forum Thread
      Answered
      Linux Software Drivers
      01 May, 2025
      I'm currently working with the ADRV9002 device configured in frequency hopping mode (GPIO index control, dual hopping, mode 3). I've encountered a consistent issue related to transmit power: Issue Details: During frequency hopping, the transmit power consistently drops by approximately 5 dB compared to operating at a single …
      iiolinux driverssoftwareADRV9002petalinuxlinuxfrequency hoppingWideband Transceiver ICRF Integrated Transceivers

    2. Having trouble with an encrypted model in LTSpice 24.1.5

      Forum Thread
      Answered
      LTspice
      31 March, 2025
      I was having no trouble with an encrypted model for the Nexperia BUK9M48-80L in older versions of LTSpice until I updated to the latest LTSpice 24.1.5. I am trying to understand what went wrong, or how to get their model to work again. LTSpice seems to not …
      simulationsoftwareLTspice 24.1.5LTspicemodel

    3. Can we assure the status of Z and Y when VCC decrease below 4.5V?

      Forum Thread
      Answered
      Interface and Isolation
      25 March, 2025
      … power down period? For example, if DE is kept low, Z and Y are in high-Z mode when VCC is between 4.75V and 5.25V, then we power down the device, can we assure Z and Y are still in high-Z mode when VCC is between 0 …
      hardwareRS-232 / RS-422 / RS-485 / RS-562ADM1491ERS-485 and RS-422

    4. AD9522-5 as PLL: not locking

      Forum Thread
      Answered
      Clock and Timing
      24 March, 2025
      Dear community, We designed a board that included a AD9522-5 chip to generate a 10-MHz clock from a reference with the same frequency. In fact, we chose it for its Zero-Delay feature. However, the loop seemed unstable because the PLL periodically entered and exited the lock condition …
      Clock Generation DevicesClock Generation and DistributionhardwareExternal VCO/VCXOAD9522-5

    5. LTspice 24.1.5 fails to simulate LTC1043 example circuit

      Forum Thread
      Answered
      LTspice
      20 March, 2025
      I hit a problem when trying to simulate the LTC1043 example circuit with LTspice 24.1.5. I got an error message saying: C:\Users\PWI\AppData\Local\LTspice\examples\Applications\LTC1043.net(16): Infinite recursion is not allowed..lib LTC1043.net^^^^^^^^^^^^^^^^ On a computer where LTspice had never been …
      Operational Amplifiers (Op Amps)software24.1.5Analog Functionsltc1043LTspiceSwitched Cap Building BlocksLow Noise Op Amps (= 10nV/vHz)LTspice model

    6. ADF4110/1/2/3 reference input sensitivity - why is it 3.0Vpp min @AV DD = 5 V, while it is 0.4Vpp min at 3.3V? Why so extremely different?

      Forum Thread
      Answered
      RF and Microwave
      10 March, 2025
      https://ez.analog.com/rf/f/q-a/165134/adf4113-convert-v-to-dbm also indicates that the sensitivity is similar, is 3.0V really correct? Regards, Alexander
      Datasheet/Specs

    7. Tx 50 Ohm different line

      Forum Thread
      Answered
      Design Support AD9361/AD9363/AD9364
      26 February, 2025
      … 100 ohm differential?Otherwise 50 ohm? Q2.I follow up following fabraction table to calculate the Tx output 50 Ohm different line on layer 10 which get w/s=35/5 mil.Can I layout with w/s=35/5 mil for Tx 50 ohm differential line on our board?
      hardwaread9361Wideband Transceiver ICRF Integrated Transceivers

    8. The four channels lose in-sync every 5 seconds

      Forum Thread
      Answered
      Precision ADCs
      19 February, 2025
      I have set DIF_reset and mute odr based on the proposal of multi-device synchronization.I do not know how to resolve the problem.Can you give some suggestions?
      softwareAD4134Simultaneous Sampling A/D ConvertersPrecision A/D Converters

    9. Need Help with 5.1 Optical Input to I²C Conversion Solution

      Forum Thread
      Answered
      Audio
      17 January, 2025
      Hello, I am working on an audio system that requires a module or board capable of the following: Input: 5.1-channel optical (SPDIF) input, supporting compressed formats like Dolby Digital or DTS.Output: Conversion of the decoded audio data into an I²C interface for integration with other components in …
      Audio Signal ProcessorsspdifAudio Productshardwaredolby 5.1 and dts 5.1 decode license infoI2S audio signalsSigmaDSP Audio ProcessorsaudioAudio CODECs

    10. UART and SPI (or mayby any two non-DMA interfaces) conflict in same Blackfin 561 core

      Forum Thread
      Answered
      Blackfin Processors
      13 January, 2025
      I try to use two interfaces to work together: UART and SPI-slave. For the B core, I have UART initialization: void uart_init(unsigned int divisor){ packet_ready = false; com_init(divisor); *pILAT = *pILAT | EVT_IVG8; // clear pending IVG7 and IVG8 interrupts *pSICB_IAR3 = Peripheral_IVG( 28, 8); *pUART …
      Audio Signal ProcessorssoftwareBlackfin Embedded ProcessorsBF561_UART_SPI_CONFadsp-bf561VisualDSP++ 5.1.2.0