Magnifying Glass Icon close icon

Filters

Filter Icon

Filters

Expand or Collapse Filter Icon
Expand or Collapse Filter Icon
Product Categories
Expand or Collapse Filter Icon
Industry Solutions
Expand or Collapse Filter Icon
Site Section
  • 1
  • 4
  • 1
Expand or Collapse Filter Icon
Result Type
  • 16
  • 3,343
  • 52,569
  • 440,289
  • 284,456
  • 714
Expand or Collapse Filter Icon
Groups, Forums & Libraries
  • 10,715
  • 9,374
  • 9,917
  • 13,372
  • 10,928
  • 22,723
  • 8,406
  • 9,531
Expand or Collapse Filter Icon
Author
  • 55,222
  • 2,543
  • 3,350
  • 6,338
  • 2,572
  • 5,301
  • 5,703
  • 3,722
Expand or Collapse Filter Icon
Tag
  • 29,097
  • 28,436
  • 27,692
  • 20,424
  • 17,036
  • 14,674
  • 14,459
  • 12,836

Results on Analog.com

1
Newest First

Sort by

  • Site_section:Resource Library
  • Product_categories.lvl0:Switches and Multiplexers > Buffered Analog Multiplexers
Clear All Filters Icon
External Link Icon Right Arrow Icon External Link Icon External Link Icon Tag
  1. Precision Products and Signal Chain Solutions: Selection Guide 2019
    Product Selection Guide
    We have created this combined precision signal chain selection guide to give you quick and easy access to information on our latest industry-leading, high performance products so you can find the best and newest parts for your complete signal chain designs.

    PDF

    13.38 M

  • <<
  • <
  • 1
  • >
  • >>

Results on EngineerZone

781,390
    Clear All Filters Icon

    1. Capacitors not removing DC component after new update.

      Forum Thread
      Answered
      LTspice
      10 May, 2025
      Hi, I wasn't sure where to post this. If I shouldn't post here, please let me know where could I do so. I wanted to let you know of a current bug in the latest LTSpice version. Now, capacitors wont filter DC components unless there's something connected …
      software24.1.7LTspicebug

    2. Feature Request

      Forum Thread
      Answered
      LTspice
      10 May, 2025
      Request a function to auto-generate "fixed" net names. Net names are automatically assigned when a new wire is added to a circuit. However, the net names are dynamically changed when new wires are added. A feature to optionally auto-generate "static" or "fixed" net names that do not change …
      software24.1.x

    3. CFR hard clipping

      Forum Thread
      Answered
      Design Support ADRV9026/ADRV9029
      09 May, 2025
      Regardless of the EVM performance, is it possible to enable only the hard clipping and not enable the other three CFR engines? adi_adrv9025_CfrHardClipperConfig_t cfrHardClipperConfig; cfrHardClipperConfig.cfrHardClipperEnable = 1; cfrHardClipperConfig.txChannelMask = tx_mask; cfrHardClipperConfig.cfrHardClipperThreshold = 0.5; printf("chan: %d th: %f \n", cfrHardClipperConfig.txChannelMask , cfrHardClipperConfig.cfrHardClipperThreshold); if (ADI …
      softwareadrv9025

    4. Technical Support for AD9576

      Forum Thread
      Answered
      Clock and Timing
      09 May, 2025
      Dear AD Team, We want to use for 10MHz to 16.369MHz conversion operation in My Project. What is hardware configuration needs to follow and software driver to configure the PLL. Is it have any preset configuration needs to follow? How much complexity in the software and we are using …
      Clock Generation and DistributionhardwareClock Distribution Devicesclock and timingAD9576

    5. RXD pin is low when DE&RE is driven High

      Forum Thread
      Answered
      Interface and Isolation
      08 May, 2025
      pins DE and RE are connected together, when transmiting on tx and both pins are high the Rx falls to GND causing frame error at uart. is there a reason for this behavior? is it intended or a bug?
      hardwareadm2483Digital Isolation TechnologyADM2483BRWZIsolated RS-485rs485 transceivers

    6. School Project

      Forum Thread
      Answered
      LTspice
      08 May, 2025
      Design an op amp circuit to perform the following operation: vo = 3.5v1 - 2.5v2. All resistances must be <= 100k. The power supply should be +15V and -15V. Let v1 = 2V and v2 = 1V. I need help designing an op amp on LTSpice for a school project that counts as …
      Operational Amplifiers (Op Amps)simulationsoftware24.1.1LTspice

    7. AD9364 start-up RF spike

      Forum Thread
      Answered
      Design Support AD9361/AD9363/AD9364
      07 May, 2025
      When initialising the AD9364, I see a rather strong RF spike at the expected TX frequency for a few milliseconds (around 0 dBm), which then descends to the expected level.My init sequence after FIR setup, sampling freqs etc is in general terms:SetAfcDefault();SetRxFrequency(rxFreq);SetTxFrequency(txFreq);SetTxAttenuation(txAttn …
      hardwareWideband Transceiver ICrfad9364RF Integrated Transceivers

    8. how to receive undetermined length data through UART?

      Forum Thread
      Answered
      Precision Microcontrollers
      07 May, 2025
      I want to receive data with UART. The data could be 10 byte, 20 byte, 30 byte. COMRX is only 8 bit=1byte. When COMRX is full, it will generate an interrupt, then I'll read COMRX in the interrupt service routine software code. But how can I know the …
      softwaremicrocontrollersPrecision Microcontrollersaducm360

    9. ESD Protection

      Forum Thread
      Answered
      Interface and Isolation
      07 May, 2025
      In the block diagram below, I'm using an isolated RS422(ADM2390EBRWZ) transceiver. My system includes the diodes shown in the diagram, but there is no GDT between the two isolated grounds. During ESD testing with an ESD gun, the TVS diodes were ineffective, and my system suffered significant damage …
      adm2490ehardwareDigital Isolation TechnologyIsolated RS-485ADM2490EBRWZ

    10. Applying Hamming windowing to adc data before FFT block

      Forum Thread
      Answered
      FPGA Reference Designs
      07 May, 2025
      hi, i am trying to implement hamming windowing for adc data before fft block, i have generated .coe files using python hamming function and created BROM IP core and loaded the .coe file. please refer attached image. i am not getting correct data, how to verify this design and any …
      software2018.3