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- Technical ArticlesOct 1, 2019JESD204B is a 12.5 Gbps serial interface standard for high speed, high resolution data converters. Already, devices from converter manufacturers are beginning to make their way into the market, and it is expected that the number of JESD204B-enabled products will increase tremendously in the near future.
- Analog DialogueThis article discusses design techniques for reliable integrated digital interfaces including the digital power-supply level and sequence I/O state during turn on interface timing signal quality and errors caused by digital activity.
- VideoMar 11, 201441:32This webcast provides an overview of the JESD204 standard from its original version up to the current "B" revision. Common "high-performance metrics" that are associated with high speed serial interfaces such as JESD204 will be described. 04-18-12
- Technical ArticlesAug 1, 2015As high speed signal acquisition applications using multiple analog-to-digital converters (ADCs) increase in complexity, each converter’s complementary clock solution will dictate the dynamic range and capacity of the system’s potential.
- VideoOct 17, 20121:35Start prototyping fast with the JESD204B-compliant AD9250 A/D converter. Available on a FMC with online software and support, this is a faster, easier way to connect your Xilinx Kintex and Virtex FPGAs with ADI’s JESD204B data converters.
- FPGA Interoperability Reports
- VideoApr 20, 20122:49This video will provide viewers an introduction to EYE diagram measurement in JESD204B interfaces.
- Technical ArticlesAug 1, 2019Many communications, instrumentation, and signal acquisition systems require the ability to simultaneously sample analog input signals across multiple analog-to-digital converters (ADCs).
- Technical ArticlesFeb 1, 2014For high speed signal sampling and processing applications that need an array of synchronized analog-to-digital converters (adc), the ability to deskew and match latency variation across the converters is paramount.
- Technical ArticlesOct 1, 2016In this article, an ultrasound receiving channel design solution based on an octal AFE with digital demodulator and JESD204B interface is introduced, which effectively resolves the design difficulties caused by the large data rates and complex physical connections of the system.
