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- Technical ArticlesMay 1, 2021This article presents experimental results utilizing a 16-channel transmit and 16-channel receive subarray in which all transmit and receive channels are calibrated using hardened DSP blocks within the digitizer integrated circuit (IC).
- Application NoteThis application note looks at some basic filter key specifications concepts.
- Application NoteAs higher resolution data converters capable of direct IF-sampling come to market, system designers need help making performance/cost trade-off decisions on low jitter clock circuits.
- Analog DialogueBoth high speed and noise filtering can be obtained by combining two PLLs: a low-frequency device with narrow loop bandwidth for jitter cleaning followed by a high-frequency device with a wider loop bandwidth.
- Technical ArticlesApr 18, 2023Phased array calibration generally focuses on optimizing the fundamental signal of interest. This article presents a method to improve spurious performance once the phase calibration for the desired signal is known.
- InformationalThe JESD204 and the JESD204B revision data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays).
- Technical ArticlesJan 1, 2017High speed analog-to-digital converters (ADCs) are by definition devices that sample an analog signal and, as such, must have sample clock inputs.