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Results on EngineerZone

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    1. AD9361 LVDS INVERT

      Forum Thread
      Answered
      Design Support AD9361/AD9363/AD9364
      13 April, 2025
      I had design a board. only TX port invert P and Q.and as a result. I got tuning tx fail under plutosdr fw. when I set adi,lvds-invert1-control = <>; adi,lvds-invert2-control = <>; the result is the same. I see the reference.I think I set the …
      softwaread9361Wideband Transceiver ICRF Integrated Transceivers

    2. ADAS1000 SPI communication issues using EVAL-ADAS1000SDZ

      Forum Thread
      Answered
      Precision ADCs
      11 April, 2025
      I am attempting to use the ADAS1000 via the primary SPI interface. But I am not seeing the responses I expect. My MCU is a Nordic nRF52840 running the Zephyr OS. My development setup consists of the MRC's Dev Board connected to the Analog Devices ADAS1000SZ Dev Board using …
      Biopotential Sensorshardwarespi problemadas1000Bio-Sensors

    3. Frontend AGPIO with C99 example

      Forum Thread
      Answered
      TES GUI & Software Support ADRV9001 – ADRV9007
      11 April, 2025
      Hi, I am working with ADRV9002-ZC706 evaluation, TES version 0.14.0, I am working with AutoTDD example and I want move TxEnable signal to the external FrontEnd. With Simple Code C99 , I generate my example application, if I run the application I can see the TDD RF signal …
      0.14.0softwareADRV9002Wideband Transceiver ICRF Integrated Transceivers

    4. ad9363 tune delay fail but rx ok

      Forum Thread
      Answered
      Design Support AD9361/AD9363/AD9364
      11 April, 2025
      hello. I have degign a board with zynq010 and ad9363. My problem is when in cmos mode. the ad9363 works fine. in lvds mode. the rx path works fine,I check it by send a signal from outside and the rx signal looks ok : but when I connect rx1 to …
      softwaread9361ad9363Wideband Transceiver ICRF Integrated Transceivers

    5. AD9231 interleaved output mode

      Forum Thread
      Answered
      High-Speed ADCs
      11 April, 2025
      Hi ADI team, Follow figure 3 on datasheet, I see in interleaved output mode, we have double data rate output respective with DCO. I want to understanding how about input sample between channel A and B with input CLK?At the same time, sampling between channel A and B occurs …
      Datasheet/Specsad9231High Speed A/D Converters &gt;10 MSPSStandard High Speed A/D Converters

    6. Request for Mechanical Design Guidance – Wearable Optical Sensor Integration

      Forum Thread
      Answered
      Other Products (EN)
      11 April, 2025
      We are designing a wearable health monitor in a watch form factor, featuring an optical sensor (LED + PD) and ECG electrodes. To address light leakage and ensure good skin contact, we're exploring two design options: 1. Flat-shaped cover glass – We are seeking guidance on the recommended height at …
      hardwareOptical AFEsOptical Sensing TechnologyMAX86176

    7. LT1997-1 : Temperature coefficient of Vos

      Forum Thread
      Answered
      Differential Amplifiers and ADC Drivers
      11 April, 2025
      I have a question about the temperature coefficient of the output offset voltage of LT1770-1.On page 4 of the datasheet, there is an entry for ⊿Vos/⊿T, which states &plusmn;0.2uV/degree (typical) and &plusmn;1uV/degree (maximum), But it does not indicate how much the gain is.The …
      Datasheet/SpecsSpecialty AmplifiersDifference AmplifiersLT1997-1

    8. Question about supported Bitclock values in ADAU1860 using LARK STUDIO

      Forum Thread
      Answered
      Audio
      10 April, 2025
      Hi ADI, I can see Serial Audio Port tab in lark studio which has capability of generation of bit clock values of 3072,6144,12288, 24576. Is there any option to choose different clock, let say for 16 bit I2s 48K need 16*2*48000=1536khz as bit clock. It …
      hardwareIntegrated/Special Purpose A/D Convertersadau1860Audio CODECs

    9. Concerns about the differential clock input to AD9652 chip

      Forum Thread
      Answered
      High-Speed ADCs
      10 April, 2025
      Hi team, I am using AD9652 ADC chip in my project. I have two questions in my mind regarding input clock to AD9652. 1.Should I provide clock input to be free running or can I generate from my FPGA. 2.Is it necessary to have 1.24 Ghz clock …
      hardwareclockHigh Speed A/D Converters &gt;10 MSPSStandard High Speed A/D Convertersad9652

    10. Supplying up to 30V with the MAX17291B

      Forum Thread
      Answered
      Power Management
      10 April, 2025
      The datasheet of the MAX17291B tells that the maximum output voltage of this module is 20V. I would like to supply variable output voltages that I configure using a PWM input signal in the module. I would like to get voltages that range between 5-30VIn the following image of …
      hardwareStep-Up (Boost) RegulatorsMAX17291Boutput voltagepwmpowerInternal Power Switch Boost Regulators