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  1. AD9173
    Recommended for new designs
    Product
    Standard High Speed D/A Converters
    Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
    AD9173

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  2. AD9172
    Recommended for new designs
    Product
    Standard High Speed D/A Converters
    Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
    AD9172

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  3. AD9176
    Recommended for new designs
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    Standard High Speed D/A Converters
    Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers
    AD9176

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  4. AD9175
    Recommended for new designs
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    Standard High Speed D/A Converters
    Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers
    AD9175

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  5. AD9171
    Recommended for new designs
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    Standard High Speed D/A Converters
    Dual, 16-Bit, 6.2 GSPS RF DAC with Single Channelizer
    AD9171

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  6. AD9177
    Recommended for new designs
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    Standard High Speed D/A Converters
    Quad, 16-Bit, 12 GSPS RF DAC with Wideband Channelizers
    AD9177

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  7. AD9174
    Recommended for new designs
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    Standard High Speed D/A Converters
    Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
    AD9174

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  8. AD9164
    Recommended for new designs
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    Standard High Speed D/A Converters
    16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer
    AD9164

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  9. AD9166
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    Standard High Speed D/A Converters
    DC to 9 GHz, Vector Signal Generator
    AD9166

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  10. AD9694
    Recommended for new designs
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    Standard High Speed A/D Converters
    Quad 14-Bit, 500 MSPS, 1.2 V/2.5 V Analog-to-Digital Converter
    AD9694

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Results on EngineerZone

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    1. Trying to implement jesd204b protocol between ADRV9009 and ZC706 using TCL files provided by EngineerZone.

      Forum Thread
      Answered
      FPGA Reference Designs
      23 February, 2024
      Hi, I have downloaded the TCL files from GITHUB available in the following link for building sample vivado example project for ADRV9009 ON ZC706 Releases · analogdevicesinc/hdl (github.com) Tools used: 1.Vivado 2019.1 2.Tried in both windows and Linux environment. Trying to implement but couldn't figure …
      jesd204softwarezc706adrv9009Vivado2019.1Wideband Transceiver ICrf and microwaveRF Integrated Transceivers

    2. Using JESD204 Analog Drivers for a custom board

      Forum Thread
      Answered
      Linux Software Drivers
      28 November, 2022
      Hi everyone, I am using AD JESD204 IP's to implement the interface on a custom board. I have tested the design with a baremetal program and everything works fine. Now, I want to integrate my design with an embedded Linux to use the JESD204 drivers, I use petalinux to …
      jesd204software2021.1driverslinux

    3. AD9081: Unable to get JESD204C ADC mode 27.0 , DAC mode 20 working.

      Forum Thread
      Answered
      Software Interface Tools
      24 October, 2022
      … adc.decimation sys.converter.dac.sample_clock = 4000000000 / sys.converter.dac.interpolation mode_tx = "20" mode_rx = "27.0" So I am using the following JESD204C setups: 'jesd_adc': {'CS': 0, 'F': 3, 'HD': 0, 'K': 256, 'L': 8, 'M': 4, 'Np': 12, 'S': 4, 'bit_clock': 12375000000.0, 'converter …
      jesd204softwarepyadi-jifpyadi-jif (latest)zcu102AD9081zynqmp-zcu102-rev10-ad9081 reference designAD9081-FMCA-EBZHigh Speed A/D Converters >10 MSPSMixed-Signal Front Ends (MxFE)

    4. How to control JESD204B in AD9081

      Forum Thread
      Answered
      Mixed-Signal Front Ends (MxFE)
      01 August, 2022
      HI, I am having trouble controlling JESD204B in AD9081. The JESD204B Setting for controlling the four DACs is as follows. JESD MODE 16L 8M 16F 4S 1K 32N 16Daterate 250MSPSLanerate 10GHzTOTAL_INTEPOLATION 12x4 The JESD204B structure I think is as shown in the figure. 　 (L = 8, M = 16, F = 4 …
      jesd204softwareAD9081jesd204b

    5. JESD204 setting for ZCU102+AD9083 HDL reference

      Forum Thread
      Answered
      FPGA Reference Designs
      16 February, 2022
      Hi all, I'm using AD9083 on ZCU102 HDL reference design (wiki.analog.com/.../ad9083_evb_reference_hdl) with . Linux driver, and trying to modify it so that the sampling rate per converter becomes 160Msps as follows. AD9083 EBZ setting in dtsi: - CIC decimation: bypassed - J decimation: 12 - PLL_ref …
      jesd204hdl reference designzcu102High Speed A/D Converters >10 MSPSStandard High Speed A/D ConvertersAD9083

    6. JESD204 FSM Topology Question

      Forum Thread
      Answered
      Linux Software Drivers
      4/1/2021 2:19:42 PM
      … on only the TX transport layer axi_adrv9009_core_tx, and the axi_adrv9009_core_tx entry DOES have a jesd204-device property. &trx3_adrv9009 { jesd204-device; #jesd204-cells = ; jesd204-inputs = , , ; /delete-property/ interrupts; adi,jesd204-framer-a-lmfc-offset = ; }; &axi_adrv9009_core_tx { jesd204-device; #jesd204-cells = ; jesd204-inputs …
      jesd204devicetreeadrv9009fmcomms8Wideband Transceiver ICRF Integrated Transceivers

    7. ad9680 failed to enable JESD204 link for hdl_2019_r2 branch

      Forum Thread
      Answered
      FPGA Reference Designs
      26 February, 2021
      … vivado hls 2019.1 - petalinux 2019.1 An image was successfully built without errors. But when I boot this image, the ad9680 failed to enable JESD204 link. This is shown in the following dmesg log. Thus I can not get any signals on iio scope display. I appreciate any suggestion …
      ad9680Clock Generation Devicesad9523jesd204Standard High Speed D/A ConvertersClock Generation and Distributionspi problemadv7511clock and timingHigh Speed D/A Converters =30MSPS

    8. JESD204B/C Mode Selector Tool

      Forum Thread
      Answered
      Mixed-Signal Front Ends (MxFE)
      24 January, 2021
      Hello there,Datasheet for AD9082 mentions about JESD204B/C Mode Selector Tool.Could you please share the link where I can download it?Cheers,Taras.
      jesd204AD9081High Speed A/D Converters >10 MSPSMixed-Signal Front Ends (MxFE)AD9082

    9. Connecting MxFE JESD204B in Loopback/No Processor

      Forum Thread
      Answered
      Mixed-Signal Front Ends (MxFE)
      02 December, 2020
      Hello there, I was interested in seeing if we could naively connect integrated transceivers together via JESD240B, but without having a processor in between them. Is there any reason I would need a FPGA/Processor in between? Specific use case is having AD9081 or AD9082 connected "back to back" on …
      jesd204AD9081High Speed A/D Converters >10 MSPSMixed-Signal Front Ends (MxFE)AD9082

    10. ad9680 jesd204b fpga

      Forum Thread
      Answered
      High-Speed ADCs
      13 July, 2020
      The devices I am using are the ad9680 evaluation board and the zcu102 evaluation board, and the two are connected through the FMC connector and the JESD204B protocol.I want to do the following. After powering on, don't give ad9680 the sampling clock first, and then wait for some …
      ad9680jesd204sampling clockHigh Speed A/D Converters >10 MSPSStandard High Speed A/D Convertersfpga