Low-Cost, Complete Power Solution for Powered Devices Includes a 12V Buck Converter

The circuit of Figure 1 is the complete powered device (PD) with a DC-DC converter providing up to 0.85A at 12V. Although the MAX5953A contains both high- and low-side switching FETs, the internal low-side FET cannot be configured as a synchronous catch diode. Consequently, the buck converter uses only the high-side FET. Because the current-limiting circuit within the IC operates using voltage-drop information derived from current flow through the low-side FET, this circuit contains no automatic current limiting. The included fuse, F1, provides short-circuit protection at startup.

The MAX5953A provides the following features:

1. TVS diode D1 protects against transient voltage spikes and against reverse-voltage application.
2. The circuit operates in three modes depending on the input voltage: PD detection signature, PD classification, and PD power. All voltage thresholds operate with or without the optional diode bridge, while complying with the IEEE 802.3af standard.


• In PD detection mode, the power source equipment (PSE) applies two voltages at V_IN in the 1.4V to 10.1V range with a minimum step of 1V, and records the corresponding current measurements at those two points. The PSE then computes ΔV/ΔI to ensure the presence of the 25.5kΩ signature resistor, R1. Most of the MAX5953A's internal circuitry is off, and the offset current is below 10µA.
• In classification mode, the PSE classifies the PD based on the power consumption required by the PD. Resistor R2 (255Ω) signals the PSE that this PD will operate in Class 3 at a maximum power of 6.49W to 12.95W. Classification current is turned off when the device enters the power mode.
• When V_IN rises above the 38V UVLO threshold, the MAX5953A enters the power mode and gradually turns on the internal MOSFET to limit inrush current.


3. When the slow turn-on is complete and V_OUT - V_EE = 1.23V, P_GOOD goes to open-drain mode. The soft-start capacitor C15 charges from an internal 33µA pull-up current to provide a soft start of the DC-DC converter. The DC-DC converter is prevented from operating until V_OUT = -30V (with respect to V+), as set by resistor voltage-divider R6/R7 and the 1.33V DCUVLO threshold.
4. Because the Class 3 power limit is 12.95W, the load is limited to 0.85A at 12V with a power conversion efficiency of 80%.

Hot-Swap Circuit Description

The default UVLO turn-on voltage is 38.6V, and the default turn-off voltage is about 30V. The UVLO turn-on and turn-off can be set to any value between 12V and 67V by connecting a resistor voltage-divider between V+ and VEE with tap at UVLO.

Once the UVLO is reached, an internal FET is slowly turned on by charging the FET gate with a 10µA current. This slow turn-on minimizes charging current of the 100µF C6. In this circuit, the hot-swap output voltage at OUT falls at a rate of ≈910mV/ms, and the fall begins ≈8ms after voltage is applied at the input. See Figure 2.

CH1 = V_SS, CH2 = V_OUT

PWM Circuit Description

The DC-DC converter is a typical buck converter that uses the internal high-side FET and an external Schottky catch diode. The operational input range is 30V (set by the resistive-divider at DCUVLO) to 60V. This range corresponds to a step-down ratio of 2.5:1 minimum to 5:1 maximum. The resultant duty cycle is 20% to 40%. The switching frequency is set to 532kHz by R4 and C4 to provide a minimum ON pulse width of ≈420ns to keep switching losses low.

Soft-start is provided by a combination of timing operations: by limiting the feedback voltage at OPTO to no more than 1.45V above the voltage at C_SS, and by charging the capacitor at C_SS by an internal 33µA current source. C_SS is initially clamped to GND by P_GOOD, but P_GOOD is released as the hot-swap function is completed when OUT is within 1.2V of V_EE. This procedure allows a slow ramp on the feedback signal at startup, slowly increasing the duty cycle to prevent output overshoot. The soft-start feature is apparent by the slope on the OPTO pin at startup (Figure 3), and the ramp becomes operational as V_OPTO reaches ≈2V, as shown in Figure 4 under high load and Figure 5 under low load.

CH1 = V_OPTO, CH2 = V_CSS; C_SS = 470nF

CH1 = V_OPTO, CH2 = V_RAMP, I_LOAD = 400mA

CH1 = V_OPTO, CH2 = V_RAMP, I_LOAD = 50mA

The controller operates in voltage mode with the voltage feed-forward ramp set by R3 and C3. The OPTO signal is compared with the voltage on RAMP.

Output-Voltage Overshoot at Startup

A soft-start capacitor (C_SS) value of 470nF minimizes overshoot to 1% or less, as shown in Figure 6. Lower C_SS values are only mildly effective in controlling output-voltage overshoot at turn-on, as shown in Figure 7 where overshoot is 7.7% when CSS = 100nF. Smaller C_SS values allow faster startup, but at the expense of increased output overshoot at turn-on.

CH1 = V_OUT, CH2 = V_CSS, C_SS = 470nF, R_LOAD = 30Ω (I_OUT = 400mA at 12V), Overshoot ≈ 0

C_SS = 100nF

Current Limiting

Although the MAX5953 integrates both high- and low-side FETs, the low-side FET is intended for transformer-coupled isolated forward or flyback circuits. The high- and low-side FETs are ON simultaneously, and current sensing is normally provided by sensing a voltage drop across the low-side FET. Because the low-side FET is not used, no current sensing is performed in this circuit. A fuse is provided to prevent damage to the MAX5953 and its internal pass FETs when a short circuit occurs. However, the fuse has limited effectiveness in protecting against output short circuits once the DC-DC converter has started. This is because the pass device may fail during the thermal time lag of the fuse.

Load Transients

Figure 8 shows load transients when switching between 1/2 load and full load. A fixed 400mA load is present, and a pulsed 400mA load is added in parallel at the output. If load is pulsed from 0mA to 400mA, as in Figure 8, the load transients increase considerably. However load transients are low, as shown in Figure 9, and are nearly independent of DC load current above 50mA.

CH1 = V_OUT, CH2 = ΔI_OUT, Transients = 1.2%, I_OUT = 800mA→400mA→800mA

CH1 = V_OUT, CH2 = ΔI_OUT, Transients = 5% to 10%, I_OUT = 400mA→0mA→400mA

Conversion Efficiency

The conversion efficiency varies from 71% at 250mA load current to 80.5% at 1A load current. Figure 10 shows that efficiency is > 80% at 850mA full load.

Loop Stability

The voltage-mode control loop exhibits two poles at the 4.1kHz LC_OUT (L1, C9) resonance and a zero above 4MHz due to the small ESR of C_OUT. A type-3 loop compensation is used to allow a unity-gain bandwidth above the LC_OUT resonance. Two zeros are set at 2.1kHz (R9, C14) and 4.1kHz (R11, C15) to compensate for the double pole at the LC_OUT resonance. Two poles are placed at 20kHz (R9, C13) and 125kHz (R10, C15). The closed-loop Bode plot of the control loop in Figure 11 shows a 19.4kHz unity-gain frequency with 59° phase margin.

Application

This simple buck converter is most suitable in PD applications where its low-cost nontransformer-coupled structure outweighs the possible circuit failure under applied short-circuit conditions.