Santa Fe (MAXREFDES5)

Required equipment:

• Windows^® PC with two USB ports
• Santa Fe (MAXREFDES5) board
• Santa Fe-supported platform (i.e., Nexys 3 development kit or ZedBoard kit)
• Industrial sensor or signal source

Download, read, and carefully follow each step in the appropriate Santa Fe Quick Start Guide:

• Santa Fe (MAXREFDES5) Nexys 3 Quick Start Guide
• Santa Fe (MAXREFDES5) ZedBoard Quick Start Guide
• Santa Fe (MAXREFDES5) MicroZed Quick Start Guide

The Pmod specification allows for both 3.3V and 5V modules as well as various pin assignments. This module is designed only for a supply voltage of 3.3V and uses the SPI pin assignments as illustrated on the right. The power requirements are shown in Table 1. The currently supported platforms and ports are shown in Table 2.

The Santa Fe hardware design is specifically optimized for applications that use -10V to +10V, 0 to 10V, and 4–20mA signals. Depending on the application requirements, certain portions of the circuit may be omitted. A complete discussion of what portions are needed or may be omitted follows. See the file for the schematic under the All Design Files section.

The MAX1301 (U3) is a 16-bit, successive-approximation register (SAR) ADC with unique multirange inputs capable of accepting input voltage signals up to +12.288V to -12.288V. The ADC also has integrated analog input buffers with a 17kΩ input resistance.

The first MAX9632 amplifier (U1) is optimized for low-noise, -10V to +10V input voltages. The second MAX9632 amplifier (U2) is optimized for low-noise, 4–20mA input currents. Both U1 and U2 provide high input impedance for input signals that have a large source resistance, or in the case of the 4–20mA loop, a 250Ω load resistance. Large source resistances often attenuate signals by an undesirable factor. Add an optional 500Ω series resistor in front of both MAX9632 amplifiers if input protection is desired while the Santa Fe design is not powered. The 500Ω series resistor prevents the input current from exceeding the maximum input current specification when 10V is applied at the input and the Santa Fe board has no power.

If the signal source has a significantly low source resistance compared to 17kΩ, or in the case of the 4–20mA loop, if the parallel combination of 250Ω and 17kΩ provides acceptable accuracy in the application, then U1 and U2 can be eliminated. ADC channels AIN1 and AIN3 are examples of using only the internal 17kΩ analog input buffers.

Although the MAX1301 ADC has an internal 4.096V voltage reference, for highest accuracy use the external MAX6126 (U4) voltage reference with 0.02% initial accuracy and a 3ppm/°C maximum temperature coefficient (tempco).

The MAX256 (U5) provides an isolated, functional insulation class power solution that accepts 3.3V and converts it to ±12V using an off-the-shelf TGM-H281NF Halo^® transformer with a 1:2.6 primary to secondary turns ratio plus an external on-board voltage-doubler circuit. Post-regulation is accomplished using the MAX1659 low dropout (LDO) regulators. The ±12V isolated power solution is optional and is only needed for applications that require the MAX9632 amplifiers to provide a high input impedance or when power isolation is required. If the MAX9632 amplifiers are not needed, then a single +6V isolated supply can power the entire circuit. Data isolation is also optional depending on the application and is accomplished using the MAX14850 (U9) digital data isolator. The combined power and data isolation achieved is 600VRMS.

The Santa Fe firmware design was initially released for the Nexys 3 development kit and targeted a MicroBlaze^™ soft core microcontroller placed inside a Xilinx^® Spartan-6 FPGA. Support for additional platforms may be added periodically under Firmware Files in the All Design Files section. The currently supported platforms and ports are shown in Table 2.

The firmware is a working example of how to interface to the hardware, collect samples, and save them to memory. The simple process flow is shown in Figure 2a. The firmware is written in C using the Xilinx SDK tool, which is based on the Eclipse™ open source standard. Custom Santa Fe-specific design functions were created utilizing the standard Xilinx XSpi core version 3.03a. The SPI clock frequency is set to 3.125MHz.

The firmware accepts commands, writes status, and is capable of downloading blocks of sampled data to a standard terminal program via a virtual COM port. The complete source code is provided to speed up customer development. Code documentation can be found in the corresponding firmware platform files.

The Santa Fe firmware design supports the ZedBoard and MicroZed kits. They target a hardcore ARM^® Cortex^®-A9 processor inside the Xilinx Zynq system-on-chip (SoC).

The firmware is a working example of how to interface to the hardware, collect samples, and save them to memory. The simple process flow is shown in Figure 2b. The firmware is written in C using the Xilinx SDK tool, which is based on the Eclipse open source standard. Custom Santa Fe-specific design functions were created utilizing the ARM’s internal SPI peripheral instead of the standard AXI Xilinx XSpi core to increase the maximum sampling rate to 90ksps. The SPI clock frequency is set to 3.57MHz.

The firmware accepts commands, writes status, and is capable of downloading blocks of sampled data to a standard terminal program via a virtual COM port. The complete source code is provided to speed up customer development. Code documentation can be found in the corresponding firmware platform files.

Equipment Used

• Audio Precision^® SYS-2722 signal source or equivalent
• Windows PC with two USB ports
• Santa Fe (MAXREFDES5) board
• Nexys 3 development kit
• +12V power supply (for external power testing only)
• -12V power supply (for external power testing only)

Special care must be taken and the proper equipment must be used when testing the Santa Fe design. The key to testing any high-accuracy design is to use sources and measurement equipment that are of higher accuracy than the design under test. A low distortion signal source is absolutely required in order to duplicate the results presented below. The input signal was generated using the Audio Precision SYS-2722. The analog inputs should be driven with a source and not be left floating. The FFTs were created using the FFT control in SignalLab from Mitov Software. Table 3 provides a quick reference for the AC and DC performance of each channel for both on-board isolated power and external power shown in Figures 3 through 18. All lab measurements were done at room temperature.