CN0511

RF Signal Generator Operation

High frequency RF generators, particularly at microwave frequencies, have historically been implemented using phase-locked loop (PLL) based synthesizers. DAC based DDS techniques have several advantages over PLLs: simplicity, low distortion, high-resolution tuning, and nearly instantaneous frequency, phase, and amplitude modulation. A typical DDS based signal generator is shown in Figure 2. A phase accumulator and amplitude to sinusoid converter comprise a numerically controlled oscillator (NCO). A tuning word is applied to a phase accumulator, which determines the slope of the output ramp. The upper bits of the accumulator are passed through an amplitude to sinusoid converter, and finally to a digital to analog converter.

Digital-to-Analog Converter

The AD9166 is a DC to 9GHz vector signal generator that incorporates a 6 GSPS (1x, non-return to zero mode) DAC, 8-lane, 12.5Gbps JESD204B data interface, DDS with multiple NCOs, and highly configurable digital data path that includes interpolation filters, wideband FIR85 filter, inverse SINC compensation, and digital mixers to allow flexible spectrum planning.

The AD9166 DAC core is based on a quad-switch architecture, which is configurable to double the effective DAC core update rate to 12 GSPS from a 6 GHz input sampling clock. The DAC has a noise spectral density (NSD) performance of -143 dBc/Hz with a 5 GHz single tone RF output. Spurious free dynamic range is typically 83 dB at 51 MHz, 66 dB at 451 MHz, and 38 dB at 4.051 GHz.

The differential to single-ended buffer eliminates the need for an expensive, wideband balun, and supports the full operating range of the DAC core, from DC to 9 GHz. DC-coupled outputs allow for baseband waveform generation without the need for external bias tees or similar circuitry.

The AD9166 supports return-to-zero and mix-mode operation, extending operation into the second, third, and fourth Nyquist zones. SINC roll-off for these modes are shown in Figure 3. Refer to the AD9166 data sheet for typical performance.

While intended for modulating baseband data via the JESD204B interface, the data inputs can be disabled and a DC value mixed with the NCO output. The AD9166 then functions as a single-chip, DC to 5.5 GHz, low-distortion, ultra-low phase noise RF signal generator.

Output Enable
 

In typical signal generator applications, it is important to have on/off control over the output so that any connected sensitive RF devices are not damaged. The AD9166 output can be easily configured through the TX_ENABLE pin to enable/disable the DAC output.

The TX_ENABLE pin can also be used for other functionality such as more accurate timing when enabling or disabling the DAC output, resetting the NCO phase accumulator, and even ramp up (or down) the full scale current of the DAC. For complete information on the TX_ENABLE capabilities, please view the AD9166 data sheet.

Amplitude and Frequency Control

Amplitude Output
 

The AD9166 output is a single-ended, 50 Ω (at DC), internally terminated output with a bipolar output stage for ease of interface with broadband 50 Ω environments. The equivalent output circuit is shown in Figure 4. The output stage is internally biased and terminated, with no external bias or termination components needed, and can be connected directly to downstream devices that present a 50 Ω ground referenced load.

In NCO-only mode, there are effectively two parameters that control the amplitude of the sinusoidal output:

• The DAC output current, I_OUTFS, is a digitally controlled current reference that determines the DAC full-scale output current.
• The DC Test Data word, DC_TEST_DATA, is a 16-bit digital value that is mixed (multiplied) with the NCO output in place of baseband data when in NCO-only mode.
   

The I_OUTFS value can be adjusted digitally over an 8 mA to 40 mA range by setting the ANA_FULL_SCALE_CURRENT register using Equation 1.

where:
ANA_FULL_SCALE_CURRENT is the DAC analog full-scale current adjustment value
I_OUTFS is the full-scale output current of the AD9166 in mA

Figure 5 shows the uncalibrated output of the AD9166 with various I_OUTFS and DC_TEST_DATA settings; the upper trace is with both I_OUTFS and DC_TEST_DATA set to their maximum values (40 mA and 32767, respectively). The lower blue trace has I_OUTFS set to 40 mA but the DC_TEST_DATA set to 16422, resulting in a 6 dB reduction in output power. The lower red trace has I_OUTFS set to 20 mA and DC_TEST_DATA set to the maximum value, 32767, resulting in a 6.02 dB reduction in output power.

Taking both parameters into account, the peak-to-peak output voltage of the AD9166 is then given by Equation 2.

where:
VOUT_PP is the peak-to-peak output voltage
DC_TEST_DATA is the digital scaling factor
0.8 is the gain of the AD9166 output amplifier.

The output in dBm can then be calculated by equation Equation 3:

The initial tolerance on I_OUTFS when set to 40 mA is -10.5% to +3.25%, and -7.9% to +7.1% when set to 8mA. To account for this tolerance, an initial calibration can be performed:

For a desired output amplitude of 0 dBm, set the DC_TEST_DATA to 32767, then reduce I_OUTFS until the target amplitude is reached. Typically, this would correspond to an I_OUTFS of 16mA.

Band Flatness
 

Several factors influence the CN0511 band flatness. SINC roll-off effects, as shown in Figure 3, cannot be avoided but are predictable. The output impedance also varies with frequency – it is nominally 50 Ω at DC, 23.91 – j12.44 Ω at 2.24 GHz, and 11.2 + j3.91 Ω at 4.22 GHz.(refer to the AD9166 data sheet for a Smith chart) This change in output impedance, along with any impedance mismatch at the load, causes a frequency dependent change in output amplitude.

The CN0511 frequency response was analyzed to determine the amplitude output flatness over the operating frequency range. During the band flatness test the output frequency was swept from 99 MHz to 5.8 GHz in 2 MHz steps using the AD9166 in NCO only mode.

The plot shown in Figure 5 shows several frequency sweeps using different combinations of I_OUTFS and DC_TEST_DATA output power values. Observe that the CN0511 has a relatively flat response below 2 GHz and begins to roll-off at the higher frequencies, ending with a decreased output power of around -6 dB at 5.8 GHz. It should also be noted that the plots shown in Figure 5 did not account for cable losses between the CN0511 and the spectrum analyzer.

Output Power Calibration
 

Since band flatness is a critical parameter in signal generator applications, a wideband amplitude calibration was performed to correct the amplitude errors of the CN0511. The CN0511 was swept across the entire operating frequency range in 100 MHz steps and the output power was measured using an RF power meter. This process was repeated for five different output powers, corresponding to 0 dBm, -10 dBm, -20 dBm, -30 dBm, -40 dBm to determine the calibration coefficients required to flatten the CN0511 output power response. At each frequency, the DC_TEST_DATA is set to the desired output power, relative to 32767 = 0 dBm. I_OUTFS is then increased until the correct output power is reached. The calibration coefficients are stored in the onboard EEPROM allowing the software to correct for the amplitude errors and provide an overall band flatness better than +/-0.5 dB from 0 dBm to -40 dBm.

Figure 6 shows the wideband compensated band flatness of a typical CN0511 at several different output power levels.

Frequency Output
 

The AD9166 has two implementations of the NCO function:

• A 48-bit, dual-modulus NCO for generating single tones
• A fast frequency hopping (FFH) NCO consisting of 32 NCOs, each with its own 32-bit phase accumulator
   

The main 48-bit NCO of the AD9166 is used in a dual-modulus mode to create fractional frequencies beyond the 48-bit precision. Implementation of the programmable modulus function within the AD9166 is such that the fraction, M/N, is expressed using Equation 4.

where:
f_CARRIER is the output frequency
f_DAC is the DAC sampling frequency
X is the value programmed in the Frequency Tuning Word registers
A is the value programmed in the Accumulator Delta registers
B is the value programmed in the Accumulator Modulus registers
M and N are integers, where
M < N/2
in order to comply with the Nyquist sampling requirements.

The form of Equation 4 implies a compound frequency tuning word with X representing the integer part and A/B representing the fractional part. X, A, and B are inputs to the modulus control logic in Figure 7. With a 48-bit modulus and a 12 GHz f_DAC, the frequency resolution is

The dual-modulus mode further increases frequency resolution; for more information on the Modulus NCO Mode, please view the AD9166 data sheet and application note AN-953.

In FFH NCO mode, the 32 frequency tuning words can be preloaded and any word can be selected by a single register write. Frequency resolution of the 32-bit NCOs is 2.79 Hz with an f_DAC of 12 GHz. Phase continuous, phase discontinuous, and phase coherent hopping modes are available. With a 100 MHz serial peripheral interface (SPI), hops and dwell times as fast as 260 ns can be achieved.

Figure 8 illustrates phase coherent frequency hopping. Frequency A is programmed into one NCO tuning word, and Frequency B in another. Upon enabling the phase coherent switching mode, all NCO phase accumulators begin counting simultaneously and all continue counting regardless of which individual NCO output is currently selected. In this way, the frequency of any individual NCO can be selected and is always phase coherent.

System Clocking

ADF4372 Synthesizer
 

The CN0511 uses the ADF4372 PLL that allows implementation of fractional-N or integer-N frequency synthesizers when used with an external loop filter and an external reference frequency. To achieve optimum integer boundary spur and phase noise performance, the ADF4372 uses a single-ended reference input signal, provided at REFP pin. The ADF4372 has an integrated VCO with a fundamental output frequency up to 8000 MHz using the RF8x ports. In addition, the VCO frequency is connected to a divide by 1, 2, 4, 8, 16, 32, or 64 circuit that allows the user to generate RF output frequencies as low as 62.5 MHz at RF8x.

The pair of RF8x output pins from the ADF4372 are collectors of a bipolar (NPN) differential pair driven by buffered outputs of the VCO and it also contains internal 50 Ω resistors, as shown in Figure 9. To optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable. Four current levels can be set. These levels give approximate output power levels from −4 dBm to +5 dBm.

Equation 5 is used to program the RF output frequency of the ADF4372 synthesizer.

where:
f_RFOUT is the RF output frequency
INT is the integer division factor
FRAC1 is the fractionality
FRAC2 is the auxiliary fractionality
MOD1 is the fixed 25-bit modulus
MOD2 is the auxiliary modulus
RF_Divider is the output divider value that divides down the VCO frequency

f_PFD is the frequency of the phase frequency detector which can be derived using Equation 6.

where:
REF_IN is the reference frequency input
D is the REF_IN doubler bit
R is the reference division factor
T is the reference divide by 2 bit (0 or 1)

Reference Input Frequency
 

The ADF4372 requires a reference input frequency, which is then multiplied to produce the 6 GHz AD9166 clock.

The EVAL-CN0511-RPIZ includes an onboard, ultra-low phase noise, 122.88MHz CMOS voltage-controlled crystal oscillator (VCXO) with phase noise of -166 dBc/Hz at a 1 MHz offset. The onboard VCXO enables fast bring up and evaluation of the CN0511, without the need for additional and expensive equipment.

Initial tolerance of the onboard oscillator is 20 ppm typical, suitable for many test and measurement applications. If greater accuracy is required, the VCXO clock frequency can be adjusted by the AD5693R voltage output DAC, enabling programmable clock trimming for increased accuracy.

Alternatively, the AD9166 output frequency can be trimmed by adding an offset to the frequency tuning word; the 48-bit NCO resolution provides a potential trimming frequency resolution of 42.6 μHz.

If lower system noise, tighter frequency accuracy, or more precise frequency drift is required, or if the CN0511 must be synchronized to external equipment, an external reference frequency can be applied to the clock reference connector. Any external clock source used must not exceed the 500 MHz maximum reference input frequency.

AD9166 Clock Reference Input
 

The AD9166 contains a low jitter, differential clock receiver that is capable of interfacing directly to a differential or single-ended clock source. Because the input is self-biased with a nominal impedance of 90 Ω, it is recommended that the clock source be ac-coupled to the CLK± input pins. The nominal differential input is 1 Vp-p, but the clock receiver can operate with a span that ranges from 250 mVp-p to 2.0 Vp-p.

Figure 10 shows the clock source for the AD9166 based on the ADF4372 low phase noise, low jitter PLL.

The quality of the clock source, as well as its interface to the AD9166 clock input, directly impacts ac performance. Select a clock source which exhibits the phase noise and spur characteristics to meet the target application requirements. Phase noise and spurs at a given frequency offset on the clock source are directly translated to the output signal.

The improvement in performance also depends on the phase balance of the external components as well as on the internal clock path. Process variations may result in varying phase balance across devices of the same population. Thus, if higher levels of image rejection are desired, it may be beneficial to calibrate each system independently. The AD9166 can compensate for phase imbalance through the Clock Phase Tune register. Up to 620 fF can be added to either CLK+ or CLK- in 20 fF steps.

Power Supply Architecture

The system consumes nearly 6 W when the RF amplifier is enabled which is sourced from the Raspberry Pi. Figure 11 shows the system power map which provides the information about the efficiency and the power losses for each switching and linear regulators.

The AD9166 clock supply is the most noise sensitive supply on the device, where phase noise and other spectral content are modulated directly onto the output signal. The AD9166 DAC output supply rails (+2.5 V and -1.2 V) and amplifier supply rails (+5 V, +3.3 V, and -5 V) are also areas for concern when it comes to modulating noise directing into the output signal of the generator.

The power distribution for the AD9166 and ADF4372 are shown in Table 1. The LTM8045, LTM4622, and ADP5073 switching regulators were chosen to achieve 90% efficiency based on the system load requirements. The low dropout linear regulators (LDOs), such as the ADM7150, ADM7154, and ADP1761, were chosen to supply the, DAC, amplifier, PLL, and VCO for their ultralow noise and high PSRR to achieve the best phase noise performance possible.

Power Supply Sequencing

The AD9166 requires power sequencing to avoid damage to internal circuitry. The LTC2928 power sequencer chip was used to ensure that the CN0511 powers up in the correct order as shown in Figure 12.

The LTC2928 monitors and manages up to four voltage rails, individually controlling the power on time. Other supervisory functions include undervoltage and overvoltage monitoring and reporting, as well as microprocessor reset generation for the CN0511 system.

The power-up sequence used goes in order from V1 to V3 sequentially, noting that supplies in each group should power-up and settle together. Within each group, it is a good strategy to monitor the supply with the longest settling time to ensure that all the supplies settle to their target voltage before sequencing to the next group. There are no requirements for a power-down sequence in the CN0511 application.

Thermal Considerations

The AD9166 can dissipate nearly 4 W depending on the application and configuration. The AD9166 uses an exposed die package to reduce thermal resistance and allow cooling of the die directly. A mechanical heat sink with a fan is used to dissipate the thermal heat from the package.

Figure 13 and Figure 14 show two test scenarios that were conducted for CN0511 Reference Design, one without the heat sink and the other case is with the heat sink attached. The low and high temperature reading registered in the thermal camera is the operating temperature at the surface of the CN0511. Without the heat sink, the ADF4372 device registered with the highest thermal reading that is around 86.5ºC.

And with the heat sinks attached, the LTM4622 shows the highest thermal reading that is around 60.6ºC.

Software readings were also taken from the device junction temperature for both the ADF4372 and the AD9166, as both devices have an on-chip temperature sensor which can be accessed through software. The junction temperature determines the maximum safe operating temperature for both the ADF4372 and the AD9166.

As shown in Table 2, without the heat sink, the ADF4372 has the highest temperature of 95.5ºC. While this is still below the absolute maximum operating temperature of 105ºC, ambient temperature was about 25ºC. A heat sink is required at higher ambient temperatures in order to prevent exceeding 105ºC.

With the heat sink attached, the operating temperature of the ADF4372 drops to 63.5ºC (about 30ºC lower). The significant improvement in ADF4372 junction temperature after the heat sink is placed also resulted in an improvement in phase noise by 2 dBc/Hz to 3 dBc/Hz.

Layout Considerations

Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. To improve the thermal performance of the design, thermal vias on the PCB thermal pad is used. The via diameter is between 0.3 mm and 0.33 mm and the via barrel is plated with 1 oz. of copper.

For this application, where highest performance and higher output frequencies are required, the choice of PCB materials significantly impacts results. Figure 15 shows the PCB stackup which uses Rogers 4350 dielectric material on the layers that contain RF traces to minimize the signal attenuation in signals greater than 3 GHz and to ensure the best signal integrity at the RF output.