PLL
What is a PLL?
Definition
A phase-locked loop (also phase lock loop or PLL) is a system that generates an output signal whose phase is related to its input. The two signals will have the same frequency and either no phase difference or a constant phase difference between them.
A PLL typically consists of a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The phase detector compares the reference signal with the oscillator frequency and outputs an error signal. The loop filter (usually a low-pass filter) then generates an error voltage from the error signal. The VCO then increases or decreases the oscillator frequency to lock to the input frequency. This produces an output frequency that is equal to the input frequency, and a constant phase shift (which could be zero) between the two signals. A PLL may also have a frequency divider in its feedback loop in order to create an output that is a multiple of the reference frequency instead of one that is exactly equal to it.
Block diagram of a basic phase-locked loop, with phase detector, loop filter, VCO, and optional frequency divider.
What are the three stages through which a PLL operates?
The three stages of a phase-locked loop are free running, capture, and phase lock or tracking:
- Free running- the center frequency of the PLL, which is the frequency that the VCO runs at when not locked to the input frequency.
- Capture- in order for the VCO to lock to the input frequency initially, the frequency must be within the PLL’s capture range.
- Phase lock (or tracking)- once the VCO has locked to the input frequency, it will continue to track and adjust to the input frequency as long as it stays within the PLL’s lock range. The lock range is wider than the capture range.