How to Modify the Soft-Start Profile of the DS3994

Introduction

The DS3994 is a 4-channel controller for cold-cathode fluorescent lamps (CCFLs) that backlight liquid crystal displays (LCDs). When burst dimming is used to dim the lamps, the DS3994 uses a soft-start at the beginning of each lamp burst to minimize the audible transformer noise. The soft-start profile (SSP) of the DS3994 is controlled by four Soft-Start Profile registers (SSP1/2/3/4). The SSP registers are factory-programmed and the default values suit most applications. Users can, however, modify the values of the SSP registers with the I²C interface to obtain customized SSPs. This application note describes how to do that modification.

DPWM Soft-Start

The DS3994 uses a digital pulse-width-modulated (DPWM) signal (22.5Hz to 440Hz) to provide efficient and precise lamp dimming. During the high period of the PWM cycle, the CCFLs are turned on and work at the lamp frequency. This part of the cycle is called the "burst" period. During the low period of the PWM cycle, the CCFLs are turned off and no current flows through them. By adjusting the duty cycle of the PWM pulses, one can increase or decrease CCFL brightness.

At the beginning of each lamp burst, the DS3994 provides a soft-start that slowly increases (i.e., "ramps up") the MOSFET gate-driver duty cycle. This ramping minimizes the possibility of audible transformer noise that could result from current surges in the transformer primary. The soft-start ramp profile is controlled by four SSP registers (SSP1/2/3/4). The SSP registers allow eight different MOSFET gate-duty cycles to be programmed; each programmed cycle repeats twice to total 16 lamp cycles. Although the soft-start length is fixed at 16 lamp cycles, the soft-start ramp profile is programmable and can be modified for an application.

Default Values of the SSP registers

There are eight driver duty cycles to select among when customizing the DS3994's soft-start ramp profile. Each of the four SSP registers (SSP1/2/3/4) contains two 4-bit codes that determine the MOSFET's duty cycle (MDC) for two lamp cycles at the beginning of each DPWM burst. Table 1 shows the duty cycles that correspond to each code. The soft-start gate cycles are based on a percentage of the most recent lamp duty cycle.

Table 2 shows the addresses and default values of the SSP registers.

Modifying the Soft-Start Profile

The SSP registers determine the 16 MOSFET duty cycles (MDCs) during the soft-start period to ensure that those MDCs ramp up gradually from 0 to its most recent value (or the nominal value). The time for the MDC to complete this ramp up is called the ramping time. The ramping time can be set from 0 to 16 lamp cycles in increments of two lamp cycles. The shorter the ramping time, the steeper the slope of the current envelope.

Table 3 gives the suggested values of the SSP registers for various ramping times. Users can select the appropriate SSP register values to achieve a desired ramping time. The default SSP of the DS3994 has 12 ramping cycles.

The DS3994's software can be used to program the SSP registers. The software is available for download. The software interface is shown in Figure 1. Users can use the Byte Read/Write section to adjust the SSP register values.

Figures 2, 3 and 4 show the measured CCFL current waveforms during soft-start periods with different numbers of ramping cycles and using the suggested register values in Table 3. Figure 3 illustrates the SSP with 12 ramping cycles, the default setting of the DS3994. Figures 2 and 4 correspond to SSPs with eight and 16 ramping cycles, respectively.