AN-2021: ADMV4801/ADMV4821 SPI Application Note

INTRODUCTION

This application note clarifies the features, implementations, and registers associated with the ADMV4801/ADMV4821 serial peripheral interfaces (SPI).

OVERVIEW

The ADMV4801 contains 16 independent channels and passes all 16-channel signals to or from one input/output port, RFC pin, with a combiner or a splitter. The ADMV4801 has a TRX pin to switch between transmit and receive mode, and a LOAD pin to transfer the content from holding registers to working registers.

The ADMV4821 also contains 16 independent channels, but unlike the ADMV4801, eight even channels are fed to the RFV pin and the other eight odd channels are fed to the RFH pin. Thus, the device supports horizontal and vertical polarized antennas simultaneously. The ADMV4821 also has individual control, via the TRXH and TRXV pins, for the horizontal and vertical channels to switch between transmit and receive mode. Similar to the ADMV4801, the ADMV4821 also has individual control for the load function, via the LOAD_V and LOAD_H pins, to transfer the content from the holding register to the working registers.

When referencing the load feature, function, or pins, LOAD represents the LOAD pin for the ADMV4801 and the LOAD_V and LOAD_H pins for the ADMV4821, unless otherwise noted. Similarly, when referencing the TRX pins, feature, or function, TRX represents the TRX pin for the ADMV4801 and the TRXV and TRXH pins for the ADMV4821, unless otherwise noted.

Details of how to use the LOAD pins are explained in the Hard Reset Pin, LOAD Pin, and TRX Pin section.

DIGITAL PINS

SPI PINS

The SPI of the ADMV4801/ADMV4821 allow the user to configure the device for specific operation using one of two SPI configurations: a 3-wire SPI (SCLK, SDIO, and CS) or a 4-wire SPI (SCLK, SDIO, SDO, and CS). This interface provides users with added flexibility and customization. The SPI is 1.8 V dc logic. Along with the SPI pins, there are digital pins to control other digital functions within the ADMV4801/ADMV4821.

In 4-wire SPI mode, SDIO is an SPI serial data input only and SDO is a serial data output. In 3-wire SPI mode, SDIO is an SPI serial data input/output and SDO is not used.

Place series 22 Ω resistors on SPI wires for optimum performance. Place the resistors as close as possible to the controller device of the ADMV4801/ADMV4821.

HARD RESET PIN, LOAD PIN, AND TRX PIN

The RST pin is an SPI hard reset pin and is an active low interface. Connect RST to logic high (1.8 V CMOS logic) for normal operation. RST resets certain registers (see Standard SPI Registers and SRAM Registers section for details).

Certain registers feature a LOAD pin to toggle three times to load the values from the holding registers to the working registers, so that the change can take effect in the device. This load feature enables multiple ADMV4801/ADMV4821 devices on a single array to be synchronized and the data to take effect simultaneously when the load lines are toggled. Refer to the Register Information section for details on LOAD pin toggling requirements for each register.

A rising edge of an input signal transitions for channels from receive mode to transmit mode. A falling edge of an input signal transitions from transmit mode to receive mode.

SPI PROTOCOL

STANDARD SPI PROTOCOL

The ADMV4801/ADMV4821 protocol consist of a write or read bit, followed by 15 register address (A14 to A0) bits and eight data bits. The default for both the address and data fields is organized most significant bit (MSB) first and end with the least significant bit (LSB) when Register 0x000, Bit 6 is set to 0. For a write, set the first bit to 0, and for a read, set this bit to 1. Standard Analog Devices SPI data is set to eight bits wide. See the ADMV4801 and ADMV4821 data sheets for the standard Analog Devices SPI protocol register timing diagram and for the typical timing specifications.

In addition, the ADMV4801/ADMV4821 include various registers that require wider than eight bits of data to be able to set the register values correctly. Refer to Standard SPI Registers and SRAM Registers section for details.

STREAMING MODE

While operating in standard protocol, CS can be held low and multiple data bytes can be shifted during the data part, reducing the amount of overhead associated with data transfer. Sequential addresses are assumed in ascending or descending order based on how the configuration registers are set. Streaming mode can be used to quickly load gain and phase data for the SRAM for user defined beam positions. This technique allows one or more bytes to be written to or read from without providing an address for each. See the ADMV4801 and ADMV4821 data sheets for the streaming mode write timing diagram, which show a typical write to a device streaming three consecutive addresses.

SDO READ DELAY AT HIGH SPEED CLOCK

During an SPI read operation, data is available on the SDO pin 7 ns after the 16th falling SCLK edge arrives at the SCLK pin. This SDO delay remains constant, regardless of the SCLK speed. See the ADMV4801 and ADMV4821 data sheets for the SDO delay timing diagram and two workaround if high speed clock is needed.

MULTIPLE DEVICES HARDWARE CONFIGURATION

Configure multiple ADMV4801/ADMV4821 devices by connecting all four device hardware address bits to ground (ADD0 to ADD3). This configuration assigns Address 0 to all devices and the separate CS lines select which device is active for the SPI to control for write/read operation to individual beam formers (see Figure 1). Connecting address pins to nonground supplies may cause device operation issues. This configuration also allows broadcasting to all beam formers simultaneously, if desired. Set the SPI_MODE pin on the ADMV4801/ADMV4821 to logic low for operating in standard Analog Devices SPI mode.

If all the settings across multiple devices are to be loaded at the same time, bring all CS lines to logic low and write the same beam pointer to all devices on the same SPI transaction simultaneously. Next, toggle the LOAD pin to update all devices simultaneously. If the devices are written in sequence, the user must toggle the LOAD pin each time each chip is set up.

REGISTER DESCRIPTION

STANDARD SPI REGISTERS AND SRAM REGISTERS

The ADMV4801/ADMV4821 have two types of registers: SRAM registers and standard SPI registers.

The SRAM registers are divided into paged SRAM registers and global SRAM registers.

The paged (channel) SRAM registers retain their values after software reset using Register 0x000 or via a hardware reset by pulling the RST pin to a logic low. These values are cleared after a power recycle.

The values of the global SRAM register are cleared after a hardware reset or a power recycle.

Neither paged (channel) nor global SRAM registers have specific default values, which are required on startup for normal operation. To read back from the SRAM registers, the user must send the read command twice.

In addition to the SRAM registers, the ADMV4801 and ADMV4821 include standard SPI registers that provide configurability of the device, including but not limited to

• SPI configuration.
• Transmit mode power amplifier configuration.
• Receive mode LNA configuration.
• Transmit mode common gain offset for each channel, which adjusts the common gain applied to all channels.
• Power detector and temperature sensor readback.

The standard SPI registers are also divided into paged and global registers, and have specific default values. The values of the standard SPI registers are cleared to the default values after a software or hardware reset, or a power recycle.

Most standard SPI registers are eight bits wide. However, the ADMV4801/ADMV4821 include a group of registers that are 16 bits wide. In a single SPI transaction, there are only eight bits of data to write or read. Use Address Select Register 0x08 to select either the 8 LSBs or the 8 MSBs to write or read. Set Register 0x08 to 0x01 to select the 8 LSBs. Set Register 0x08 to 0x02 to select 8 MSBs.

Certain registers feature a LOAD pin that toggles three times to load the values to the device. The LOAD pin only needs to be toggled after all registers are updated so that the data across multiple registers and channels take effect simultaneously. Users can also toggle the LOAD pin anytime, if needed.

Refer to the Register Information section for details about global and page properties, as well as LOAD pin toggling requirements for each register.

PAGED REGISTERS AND GLOBAL REGISTERS

For efficient communication to the device, each channel has a counterpart memory page, totaling 16 memory pages. Each memory page contains paged registers for the corresponding channel settings. Use Register 0x013 and Register 0x014 to select the pages (channels). Paged registers are not written or read unless the corresponding memory page is selected.

For example, Register 0x200 is a paged register. To write to Register 0x200 in all channels, first set both Register 0x013 and Register 0x014 to 0xFF.

The global registers are always accessible, regardless of page selection.

BEAM POINTER MODE AND BYPASS MODE

There are two methods to set the gain and phase for each channel in the ADMV4801 and ADMV4821: beam pointer mode and bypass mode.

In beam pointer mode, each channel memory page stores 256 user defined beam positions. For the ADMV4801, Register 0x081 is the beam pointer register that recalls (points to) the specific beam position to apply to the device. For the ADMV4821, Register 0x081 is the beam pointer register for eight vertical channels and Register 0x082 is for eight horizontal channels.

Each beam position contains phase and gain settings and can be loaded for either transmit or receive mode, regardless of the current operation mode. The LOAD pin is toggled three times to load the beam position settings to the selected channels simultaneously. The beam pointer method is recommended for the production environment due to its simplicity and the reduced amount of data transfer during beam position switching. The beam pointer can also be used for evaluation and characterization of the device.

The second method by which to set gain and phase for each channel is to bypass the beam pointer. In bypass mode, rather than using a predefined beam position and the beam pointer, directly program the settings for each channel. The bypass method is recommended only for evaluation to determine the phase and gain settings for each channel.

PHASE AND GAIN STATES SRAM

Understanding SRAM space in the ADMV4801/ADMV4821 is critical before beginning beam pointer and bypass mode implementation, because these registers are used in both modes.

The user must write to certain registers to achieve phase and gain control for the device. For transmit mode, there are three settings regarding phase and gain control:

• Transmit channel gain settings. The registers are paged and applied to Digital Variable Gain Amplifier 1 (DVGA 1) in transmit path by default. Each channel has an independent setting.
• Transmit common gain settings. Registers are global and applied to Digital Variable Gain Amplifier 2 (DVGA 2) in the transmit path by default. All channels use one global setting.
• Phase settings. The registers are paged. Each channel has an independent setting.

In receiver mode, there is a single digital variable gain amplifier (DVGA) and two settings regarding phase and gain control:

• For each channel, there is only one receive gain setting. The registers are paged and applied to the receive DVGA. Each channel has an independent setting.
• For phase settings, the registers are paged. Each channel has an independent setting.

To understand the RF signal path details, refer to the ADMV4801 and ADMV4821 data sheets.

Transmit and Receive Phase States SRAM

The ADMV4801 or ADMV4821 SRAM assigns a group of 16-bit data registers to store the phase states for both transmit and receive modes. Each register stores a single phase state, consisting of 7-bit I phase data (Bits[13:7]) and 7-bit Q phase data (Bits[6:0]). The I and Q phase data must be the same for one phase state. The data corresponds to actual phase degree. Phase states are the basis for phase settings and are used in both beam pointer mode and bypass mode.

Table 1 describes the phase state registers. The index is important because the phase settings use this index to recall the phase states.

There are 64 registers for each transmit and receive mode, with a total of 128 registers. Register 0x180 to Register 0x1BF are for transmit mode and Register 0x100 to Register 0x13F are for receive mode. These registers are all paged registers. For optimum initial performance, set the phase states with an identical location index to the same values across all channels.

Table 2 is the truth table for the actual phase values from 0° to 354.75° in increments of 5.625° with unity gain. Users can select any 64 phase values for the transmit mode or receive mode to create customized phase states. Each phase state requires 16-bit data. As mentioned previously in the Standard SPI Registers and SRAM Registers section, to write to 16-bit data registers, use Register 0x08 to identify which eight bits of the 16 bits to write. For example, write 0x01 to Register 0x08 before writing 8 LSBs to the phase state registers and 0x02 to Register 0x08 for the 8 MSBs.

To write to phase states registers, use the following procedure (note that this procedure uses Register 0x180 as an example):

1. Write to Page Select Register 0x013 and Page Select Register 0x014 to target all channels (set Register 0x13 to 0xFF and set Register 0x014 to 0xFF).
2. Determine the hexadecimal value for the actual phase values. For example, to set phase value to 5.625°, the MSB is 0x3F and the LSB is 0xC6. See Table 2.
3. Write the LSB to the registers (set Register 0x08 to 0x01 and set Register 0x180 to 0xC6).
4. Write the MSB to the registers (set Register 0x08 to 0x02 and set Register 0x180 to 0x3F).
5. Toggle the LOAD pin three times. For the ADMV4821, toggle either the LOAD_V or the LOAD_H pin, as needed.

Transmit and Receive Gain States SRAM

Similar to phase, the ADMV4801/ADMV4821 SRAM assigns another group of 8-bit data registers to store the gain states for both transmit mode and receive mode. Each register stores a single gain state. The gain data corresponds to actual gain levels. Gain states are the basis for gain settings and gain states are used in both beam pointer and bypass mode.

Table 4 describes the gain state registers. The index is important because the gain settings use this index to recall the gain states. Registers are eight bits wide but use only six bits.

There are 32 registers for each transmit mode and receive mode, for a total of 64 registers. Register 0x1C0 to Register 0x1DF are for transmit mode and Register 0x140 to Register 0x15F are for receive mode. These registers are paged registers. For optimum initial performance, set the gain states with an identical index to the same values across all channels.

Table 3 shows the truth table for the actual gain levels from 0 dB to 17.5 dB in increments of 0.5 dB. Users can choose any of the 32 gain levels (out of a total of 36 gain levels) for the transmit mode or receive mode to create customized gain states.

For transmit mode, only Register 0x1C0 to Register 0x1DF define the transmit channel gain states, which are applied to DVGA 1 by default. The transmit common gain is defined in other registers and discussed in the following sections.

To write to gain states registers, use the following procedure (note that this procedure uses Register 0x1C0 as an example):

1. Write to Page Select Register 0x013 and Page Select Register 0x014 to target all channels (set Register 0x13 and Register 0x14 to 0xFF).
2. Determine the hexadecimal value for the actual gain levels. For example, to set gain level to 17.5 dB, the data must be 0x23.
3. Write to the registers (set Register 0x1C0 to 0x23).
4. Toggle the LOAD pin three times. For the ADMV4821, toggle either the LOAD_V or LOAD_H pin, as needed.

BEAM POINTER MODE

Beam pointer mode can be used for both the production environment and evaluation, given the advantages of simpler and fewer data transfers between beam position switching. Beam pointer mode acts like a double pointer. The beam pointer points to the beam settings that include three categories of SRAM registers: beam position SRAM, transmit or receive SRAM, and transmit common gain SRAM (see Figure 4). Then, the beam position SRAM points to the phase and gain SRAM described in the Phase and Gain States SRAM section.

The ADMV4801 and ADMV4821 SRAMs can store up to 256 user defined beam settings.

The beam pointer registers are eight bits wide, paged, standard SPI registers. For ADMV4801, there is only one beam pointer, Register 0x081. For ADMV4821, there are two beam pointers, Register 0x081 for eight vertical channels and Register 0x082 for eight horizontal channels. The registers recall the settings and load the settings to the device until LOAD toggling takes place. When transmit or receive SRAM is set to receive mode, the transmit common gain SRAM register data is irrelevant, although beam pointer registers are paged. For optimum performance, use identical values across all channels.

Beam Position SRAM

Prior to writing to the beam pointer register, users must define the beam positions. Each channel memory page has 256 beam positions, stored in Register 0x200 to Register 0x2FF, indexed from 0 to 255. Each register is a 16-bit data paged register and stores the phase and gain states index, as shown in Figure 6. The beam positions with the same index can include different phase and gain settings for different channels.

To write the data into certain channel beam position registers, use the following procedure (note that this procedure uses Register 0x200 and Channel 0 as an example):

1. Write to Page Select Register 0x013 and Page Select Register 0x014 for targeted channels (set Register 0x13 to 0x01 and set Register 0x14 to 0x00).
2. Determine the index to recall the phase and gain states registers. For example, for Register 0x200, recall Register 0x183 as the phase setting and Register 0x1C1 as the gain setting. The phase state index is 0x03 and the gain state index is 0x01. Refer to Table 1 and Table 4.
3. Write to Register 0x008 and the 8-bit LSB of the beam position registers (set Register 0x08 to 0x01 and set Register 0x200 to 0x81).
4. Write to Register 0x008 and the 8-bit MSB of the beam position registers (set Register 0x08 to 0x02 and set Register 0x200 to 0x01).
5. Toggle the LOAD pin three times. For ADMV4821, toggle either the LOAD_V or the LOAD_H pin, as needed.

Transmit Common Gain SRAM, and Transmit or Receive SRAM

In beam pointer mode, in addition to the beam position registers, users must also define the transmit common SRAM registers and transmit or receive SRAM registers.

For transmit mode, gain is determined by both the channel gain and the common gain. For the ADMV4801, Register 0x400 to Register 0x4FF are assigned to store the transmit common gain settings (see Table 7). The beam pointer uses the index to recall the common gain settings. The registers are eight bits wide but only five bits are used. Table 5 is the truth table for the actual gain levels from 0 dB to 17 dB in increments of 1 dB.

Similarly, for ADMV4821, transmit common gain settings, Register 0x400 to Register 0x4FF, are assigned to vertical channels, and Register 0x500 to Register 0x5FF are assigned to horizontal channels (see Table 7).

The transmit common gain SRAM registers are global registers, regardless of page selection.

To write to transmit common gain settings registers, use the following procedure (note that this procedure uses Register 0x400 as an example):

1. example, to set transmit common gain to 17 dB, the data must be 0x11.
2. Write to the registers (set Register 0x400 to 0x11).
3. Toggle the LOAD line three times. For the ADMV4821, toggle either the LOAD_V or the LOAD_H pin, as needed.

The transmit or receive SRAM specifies the mode of the beam position. Register 0x600 to Register 0x6FF store the transmit or receive settings (see Table 6). These registers are global registers, regardless of page selection.

For the ADMV4801, when Bits[1:0] = 'b11, the beam position is assigned to transmit mode, and 'b00 is assigned to receive mode. For the ADMV4821, Bit 0 determines the vertical channels statuses and Bit 1 determines the horizontal channels statuses. When the bit value is 1, the beam position is assigned to transmit mode, and when the bit value is 0, the beam position is assigned to receive mode.

Beam Pointer Mode Programming Flowchart

Figure 7 shows the flowchart and register writes for beam pointer mode initialization. Page Select Register 0x013 and Register 0x14 write transactions (Register 0x13 = 0xFF and Register 0x14 = 0xFF) can be combined when continuously writing to all channels. Refer to the Register Information section for register functions and settings.

BYPASS MODE

Bypass mode (see Figure 3) bypasses the beam pointer, beam position SRAM, transmit common gain global SRAM, and transmit or receive global SRAM. Users directly program the settings for each channel. This method is straightforward and is recommended for evaluation to determine gain and phase settings for each channel. A group of registers enable bypass mode and send the settings to the device. Use the following procedure to use bypass mode:

1. Enable bypass mode by setting Paged Register 0x080 to 0x86.
2. Directly set the phase and gain settings using Register 0x86 for each channel. Register 0x86 is a 16-bit paged register. This register stores the phase and gain states index. Figure 9 shows the register bit map.
3. For the ADMV4801, directly set the transmit common gain settings by writing to Register 0x08E.
   
   For the ADMV4821, directly set the transmit common gain settings by writing to Register 0x08E (vertical channels) and Register 0x08F (horizontal channels). These registers are paged. The value is the hexadecimal representation of the common gain level shown in Table 5.
4. Directly set the transmit or receive mode by writing to Paged Register 0x85, Bits[6:5].
   
   For the ADMV4801, when Bits[6:5] = 'b11, the beam position is assigned to transmit mode, and 'b00 is assigned to receive mode.
   
   For the ADMV4821, Bit 5 determines the vertical channels statuses and Bit 6 determines the horizontal channels statuses. When the bit value is 1, the beam position is assigned to transmit mode, and when the bit value is 0, the beam position is assigned to receive mode.
5. Set Register 0x081 to 0x00 for all channels. Register 0x081 must be written before toggling the LOAD pin and after changing any of the following registers: Register 0x085, Register 0x086, Register 0x08E, and Register 0x08F; otherwise, the bypass mode does not function.
6. Toggle the LOAD pin three times. For the ADMV4821, toggle either the LOAD_V or the LOAD_H pin, as needed.

Bypass Mode Programming Flowchart

Page Select Register 0x013 and Register 0x14 write transactions (Register 0x13 = 0xFF and Register 0x14 = 0xFF) can be combined when continuously writing to all channels. Refer to the Register Information section for register functions and settings.

POWER-DOWN, POWER DETECTOR, AND TEMPERATURE SENSOR

The ADMV4801/ADMV4821 feature an on-chip temperature sensor and power detectors, which route to the on-chip ADC that provides SPI readback with eight bits of resolution. The ADC works in transmit mode only but can be read back in receive mode. Therefore, the temperature sensor and power detector data reflect the last transmit mode status only.

POWER DOWN

For transmit mode, use Page Select Register 0x013 and Register 0x014, together with Register 0x026, Bit 7, Register 0x027, Bit 7, and Register 0x028, Bit 7, to power down the corresponding channel. LOAD pin toggling is needed for the power-down function to take effect.

POWER DETECTOR

There are 16 power detectors (1 per transmitter channel) that sample the peak power coupled from the output of each power amplifier. These power detectors provide power monitoring and calibration for channel gain, as well as channel to channel gain mismatch. The power range of the power detector is programmable and can adjust the input power sense window from −15 dBm to +16 dBm. Register 0x40 to Register 0x4F are the readback registers for the power detectors from Channel 0 to Channel 15.

Refer to the ADMV4801 and ADMV4821 data sheets for power detector characteristic plots.

Use the following sequence to read back from the power detector:

1. Set Register 0x030 to 0x08 to enable the ADC clock.
2. Select the detector range for each channel by writing to Paged Register 0x027. Table 8 is the truth table for the register settings and power range. The information in this table is an approximate range division and may vary from device to device.
3. Read back the values in Register 0x40 to Register 0x4F.

TEMPERATURE SENSOR

The temperature sensor can sense from −40°C to +125°C. To convert the on-chip temperature sensor readback values to Celsius, use the following equation:

Case Temperature (°C) = 1.07 × (Temperature Sensor Value in Decimal) − 96

The temperature sensor value can be read back only when in transmit mode. Register 0x50 is used to read back the temperature sensor reading.

Use the following sequence to read back from the temperature sensor:

1. Set Register 0x030 to 0x08 to enable the ADC clock.
2. Read back from Register 0x50.

REGISTER INFORMATION

REGISTER SUMMARY

Download PDF to see table 9

REGISTER DETAILS

Address: 0x000, Reset: 0x00, Name: SPI_CONFIG_1

Address: 0x003, Reset: 0x00, Name: CHIP_TYPE

Address: 0x004, Reset: 0x00, Name: PRODUCT_ID_LOWER

Address: 0x005, Reset: 0x00, Name: PRODUCT_ID_UPPER

Address: 0x008, Reset: 0x01, Name: MSB_LSB_SELECT

Address: 0x00A, Reset: 0x00, Name: SCRATCH_PAD

Address: 0x00C, Reset: 0x00, Name: VENDOR_ID_LOWER

Address: 0x00D, Reset: 0x00, Name: VENDOR_ID_UPPER

Address: 0x010, Reset: 0x00, Name: CMD_TYPE

Address: 0x012, Reset: 0xBF, Name: Bandgap

Address: 0x013, Reset: 0xFF, Name: PAGE_SELECT_LOWER

Address: 0x014, Reset: 0xFF, Name: PAGE_SELECT_UPPER

Address: 0x023, Reset: 0x02, Name: RX_CHANNEL_CONTROLS

Address: 0x026, Reset: 0x19, Name: TX_CHANNEL_CONTROLS

Address: 0x027, Reset: 0x40, Name: TX_DETECTOR_CHANNEL_CONTROLS

Address: 0x028, Reset: 0x31, Name: TX_CHANNEL_CONTROLS_1

Address: 0x029, Reset: 0x65, Name: TX_PA_CHANNEL_CONTROLS_1

Address: 0x02A, Reset: 0x0A, Name: TX_PA_CHANNEL_CONTROLS_2

Address: 0x02B, Reset: 0x00, Name: TX_VGA_COMMON_GAIN_CHANNEL_CONTROLS

Address: 0x02F, Reset: 0x00, Name: COMMON_GAIN_POL

Address: 0x030, Reset: 0x00, Name: ADC_CLK

Address: 0x040, Reset: 0x00, Name: POWER_CH0

Address: 0x041, Reset: 0x00, Name: POWER_CH1

Address: 0x042, Reset: 0x00, Name: POWER_CH2

Address: 0x043, Reset: 0x00, Name: POWER_CH3

Address: 0x044, Reset: 0x00, Name: POWER_CH4

Address: 0x045, Reset: 0x00, Name: POWER_CH5

Address: 0x046, Reset: 0x00, Name: POWER_CH6

Address: 0x047, Reset: 0x00, Name: POWER_CH7

Address: 0x048, Reset: 0x00, Name: POWER_CH8

Address: 0x049, Reset: 0x00, Name: POWER_CH9

Address: 0x04A, Reset: 0x00, Name: POWER_CH10

Address: 0x04B, Reset: 0x00, Name: POWER_CH11

Address: 0x04C, Reset: 0x00, Name: POWER_CH12

Address: 0x04D, Reset: 0x00, Name: POWER_CH13

Address: 0x04E, Reset: 0x00, Name: POWER_CH14

Address: 0x04F, Reset: 0x00, Name: POWER_CH15

Address: 0x050, Reset: 0x00, Name: Temperature

Address: 0x080, Reset: 0x82, Name: SRAM_BYPASS

Address: 0x081, Reset: 0x00, Name: Beam pointer (ADMV4801) or BEAMPOINTER_V (ADMV4821)

Address: 0x082, Reset: 0x00, Name: BEAMPOINTER_H

Address: 0x085, Reset: 0x00, Name: BYPASS_TRX_PROGRAM_SRAM

Address: 0x086, Reset: 0x00, Name: BYPASS_BEAMPOSITION_SRAM

Address: 0x08E, Reset: 0x11, Name: BYPASS_COMMON_GAIN_SRAM

Address: 0x08F, Reset: 0x11, Name: COMMON_GAIN_BYPASS_VALUE_H

Address: 0x100 to 0x13F, Reset: 0x00, Name: RX_PHASE_SRAM_x

Address: 0x140 to 0x15F, Reset: 0x00, Name: RX_GAIN_SRAM_x

Address: 0x180 to 0x1BF, Startup: 0x00, Name: TX_PHASE_SRAM_x

Address: 0x1C0 to Address 0x1DF, Startup: 0x00, Name: TX_GAIN_SRAM_x

Address: 0x200 to Address 0x2FF, Startup: 0x00, Name: BEAM_POSITION_SRAM_x

Address: 0x400 to Address 0x4FF, Startup: 0x00, Name: COMMON_GAIN_SRAM_x

Address: 0x500 to Address 0x5FF, Startup: 0x00, Name: COMMON_GAIN_SRAM_x_H

Address: 0x600 to Address 0x6FF, Startup: 0x00, Name: TRX_PROGRAM_SRAM_x