AN-1554: Pairing the fido5100 and fido5200 REM Switches with a Host and Network Processor

Introduction

The use of industrial Ethernet devices is becoming incumbent in industrial automation and motion control applications, replacing legacy field bus connections such as the CANbus or the RS-485.

A high degree of determinism and reliability is needed to handle real-time applications, and many protocols have been introduced by major original equipment manufacturers (OEMs), such as Profinet, EtherCAT, Ethernet/IP, Sercos, and Modbus TCP. Compatibility with those protocols is an important consideration in every industrial communication design, as well as the possibility of needing updating for compatibility with future enhancements like time sensitive networking (TSN). Analog Devices, Inc., supports the most common industrial Ethernet protocols with real-time Ethernet multiprotocol (REM) switches, fido5100 and fido5200. This switch, paired with the fido1100 communication controller, enhance the programmable multiprotocol RapID platform. The fido5100 and fido5200 REM switches offer a precertified solution for Profinet IRT, EtherCAT, Ethernet/IP, Modbus TCP, and Powerlink.

This application note describes the host interface of the fido5100 and fido5200 REM switches with any microprocessor.

The memory bus interface is described, along with the additional signals needed to control the Ethernet interface. In this application note, active low signals are identified by use of an overbar following the name of the signal (for example, RESET).

Host Interface

The fido5100 and fido5200 REM switches connect to a communication processor with a host interface designed as a standard asynchronous memory bus port.

The fido5100 and fido5200 REM switches have two Ethernet interfaces each, which support a media independent interface (MII) or reduced media independent interface (RMII). Ethernet physical layers are intentionally left out of the switch itself because of the different requirements on Ethernet physical layer performance.

The general architecture is shown in Figure 2.

The host interface is either a 16-bit or 32-bit memory bus, with the possibility to multiplex address and data, reducing pin count.

Multiplex bus select (MBS) and data bus size (SIZE_32) signals select this bus mode. MBS and SIZE_32 are sampled on the rising edge of RESET signal.

Another aspect to consider is endianness, which is determined by the little endianness (LE) signal. The LE level is also sampled with the rising edge of RESET.

The switch data bus is defined as follows:

• D0 is the least significant bit (LSB).
• D15 is the most significant bit (MSB) for 16-bit bus.
• D31 is the MSB for 32-bit bus.

All control and status registers are 16 bits wide, so that even using a 32-bit bus, data must be transferred in the D15 to D0 order. For more details on how to handle endianness and for a detailed pin function descriptions, refer to the fido5100/fido5200 data sheet.

There are four bits of data for the address bus, giving access to 16 direct address registers. In case of a nonmultiplexed data bus (such as MBS = 0), the user must consider four additional pins for the address.

It is important to view the timing diagrams (see the fido5100/fido5200 data sheet), which show read and write operations for both nonmultiplexed and multiplexed mode.

In case of nonmultiplexed operations, the address setup time (t_AS) is a critical parameter for asynchronous memory accesses. Depending on the microprocessor architecture, the address lines and CS can be driven at the same time (t_AS = 0) or with a small delay between them.

With regards to nonmultiplexed operations, many Cortex^®-M4 families on the market (such as Analog Devices ADSP-CM408F or STM32F4) and Cortex-Ax families (such as the Analog Devices ADSP-SC589 and NXP imx6) drive CS and address lines with no delay. In other cases, like the Motorola 68000 architecture, CS is asserted after address lines are valid.

The fido5100 and fido5200 REM switches use the falling edge of CS to latch address lines, and a small delay t_AS is needed (minimum 20 ps).

When microprocessors assert CS and address at the same time, add a delay of several ns to CS. For example, the ADSP-CM408F drives CS to the fido5100 and fido5200 REM switches with a fast one channel noninverting buffer (typical 2.5 ns added delay).

In case of multiplexed memory access, the timing relationship between the address and ALE signal valid may also require adding a short delay on the ALE signal, depending on the processor used.

Interrupts

Three interrupt lines act as outputs for the fido5100 and fido5200 REM switches. The host microprocessor must monitor these lines.

MDIO Interface

All Ethernet physical layers require configuration and can provide status information. Many devices use a management data input and output (MDIO) interface. This communication interface consists of two lines: a data line (MDIO) and a management data clock line (MDC).

A specific communication protocol is defined by the IEEE802.3 specification.

The fido5100 and fido5200 REM switches do not drive this communication interface. The host processor must be able to manage MDIO and MDC accordingly.

Memory Requirements

Ideally, the REM switch driver needs 50 kB to 100 kB of read only memory (ROM). On the RapID platform, the fido1100 uses 46 kB of ROM.

In addition, 8 kB of RAM handles multiple packets in-flight in the processor simultaneously, based on the need for some industrial Ethernet protocols.

Pin Count

Table 1 summarizes the pin count for the configuration with the maximum pin count (125 MB/sec, nonmultiplexed bus) and the configuration with the minimum pin count (62.5 MB/sec, multiplexed bus), assuming MBS, SIZE_32, and LE are at a fixed level. In the nonmultiplexed bus, there are 45 pins, and in the multiplexed bus, there are 26 pins.

Interconnection Block Diagram

The complete interconnection block diagram between the host or network processor and the fido5100 and fido5200 REM switches, along with the two Ethernet physical layers, is shown in Figure 4. The dotted line in Figure 4 indicates the connection for multiplexed mode only. In multiplexed mode, do not connect the four address lines, only connect A02/ALE. A02/ALE has double functionality. In multiplexed mode, the A02 line acts as the ALE signal to validate address lines.

REM Switch Software Driver

The REM switch software driver provides a standard, protocol-independent interface to the fido5100 and fido5200. The software driver is used for initialization, interrupt management, timer management, and protocol-independent packet transmission and receiving.

The REM switch software driver for each supported protocol (Profinet, Ethernet/IP, EtherCAT, ModbusTCP, and POWERLINK) is available as source code.

The driver is written in C language, and the driver configures the switch for the selected protocol.

This firmware is downloaded from the host processor.

The configuration is typically performed at power-up, but the configuration can be performed at any time after a system reset.

As shown in Figure 5, the C code is organized into a set of application programming interfaces (APIs), grouped into two major functional areas: a protocol specific interface and a standard switch interface.

Any transmission control protocol/internet protocol (TCP/IP) stack can be connected to the standard switch interface, and any protocol stack can be connected to the protocol specific interface. Because the standard switch interface is common across all drivers, the user only needs to connect to the TCP/IP stack once.

The user may choose the TCP/IP stack that comes as part of the operating system (OS) of the processor development environment and the PROFINET stack from a third-party vendor.

The protocol stack is then managed by the host processor and connects to protocol specific API in the REM switch driver, while the standard switch API in the REM driver connects to the TCP/IP stack in the OS.

Because the driver has no dependencies on any operating system resources (such as no threading and semaphores), porting is limited to defining how the host processor communicates with the REM switch and some debugging options.

The porting related code (REMS_Port.h and REMS_Port.c) is in the Porting directory (/Porting/inc/ and /Porting/src/).

Those two files must be modified to support a specific hardware platform and are dependent on the host processor. The REM software driver architecture is shown in Figure 6.

Application Examples

This section contains examples of pairing microprocessor architectures commonly used in industrial applications. Refer to specific documentation provided by the respective integrated circuits (IC) manufacturers for further details.

Analog Devices ADSP-CM408F (Arm^® Cortex-M4 With FPU)

The ADSP-CM408F comes with a flexible external memory interface. The static memory controller (SMC) can be programmed to control up to four banks of external memory. Asynchronous nonmultiplexed 16-bit operations are allowed.

Table 2 shows the connections between the fido5100 and fido5200 REM switches and the ADSP-CM408F processor.

Analog Devices ADSP-SC589 (Sharc^®+ Dual Core DSP With Arm Cortex-A5)

The ADSP-SC589 is equipped with SMC to control up to two blocks of external memory. Asynchronous nonmultiplexed 16-bit operations are allowed. As suggested in the ADSPCM408F, the CS signal needs an external buffer, and the MDIO interface is managed by an embedded controller.

Table 3 shows the connections between the fido5100 and fido5200 REM switches and the dual SHARC + Arm processor.

Because the ADSP-SC589 does not have an embedded flash memory, the processor needs to program the REM switches at power-up to download code from an external ROM.

ST Microelectronics STM32F42 Family (Arm Cortex-M4 With FPU)

The STM32F42 family comes with a flexible memory control (FMC) interface allowing asynchronous, 16-bit and 32-bit multiplexed and nonmultiplexed access operations. Because FMC_NE (chip select) can anticipate address valid as much as 2 ns maximum, a longer delay might be needed on this signal.

Table 4 shows the connections between the fido5100 and fido5200 REM switches and the STM32F42 processor.

In case of multiplexed operations, an inverter is needed because FMC_NADV is an active low signal but the fido5100 and fido5200 require an active high signal to latch address. In this case, there is no need to add a delay because the t_{w (NADV)} time is sufficient for the fido5100 and fido5200 to latch address lines.

ST Microelectronics STM32F103 Family (Arm Cortex-M3)

The STM32F103 family has flexible static memory controller (FSMC) embedded, which can manage up to four memory banks of various types, SRAM included. FSMC allows asynchronous, multiplexed and nonmultiplexed 16-bit operations. Because FSMC_NE (chip select) can be asserted up to 3 ns before address lines are valid, a longer delay may be needed on this signal.

Table 5 shows the connections between the fido5100 and fido5200 REM switches and the STM32F103 processor.

In case of multiplexed operations, an inverter is needed because FSMC_NADV is an active low signal; however, the fido5100 and fido5200 require an active high signal to latch address. In this case, there is no need for adding a delay because the t_{w (NADV)} time is sufficient for fido5100 and fido5200 to latch address lines. This family of Cortex-M3 processors does not implement a MDIO interface.

Nevertheless, two GPIOs can be used instead, while the MDIO functionality must be emulate via software.

Texas Instruments AM1808 Sitara Family (Arm9)

The AM1808 is provided with an external memory interface (EMIFA) supporting asynchronous SRAM. EMIFA can manage 16-bit nonmultiplexed access. The chip select signal needs a buffer.

Table 6 shows the connections between the fido5100 and fido5200 REM switches and the AM1808 processor.

Texas Instruments TMS320F2807 Piccolo Family (32-Bit Floating Point Microcontroller)

The TMS320F2807 family comes with an EMIFA supporting asynchronous SRAM. The EMIFA can manage both 32-bit and 16-bit nonmultiplexed access. The chip select signal needs a buffer.

Table 7 shows the connections between the fido5100 and fido5200 REM switches and the TMS320F2807 processor.

This family of 32-bit processors does not implement a MDIO interface. Regardless, two GPIOs can be used for this purpose, while the MDIO functionality must be emulated via software.

NXP i.MX 6ULL Family (Arm Cortex-A7)

The i.MX 6ULL processors are equipped with an external interface module (EIM), providing 16-bit nonmultiplexed and multiplexed access to SRAMs.

Table 8 shows the connections between the fido5100 and fido5200 REM switches and the i.MX 6ULL processor.

In case of multiplexed operations, an inverter is needed because EIM_LBA is an active low signal; however, the fido5100 and fido5200 require an active high signal to latch address.

Because EIM_LBA deassertion (which becomes the latching time for address) depends on programmable parameters, take care when calculating W40A timing. A buffer may be necessary.

Timing W31 (EIM_CSx valid to address valid) is programmable and can be negative (CS asserted before address is valid). A buffer may be necessary.

Author

Matteo Crosio

Matteo Crosio began his career in Analog Devices in 2011 as Field Applications Engineer based in Italy, after 10 years covering different technical roles in the semiconductor industry. With a mixed-signal background in aerospace and telecom applications, Matteo brings a solid experience as hardware and FPGA designer, with a special focus on time synchronization. As part of the European Sales organization, he’s now supporting the EMEA region on wired communication technologies.