Design a PLL Filter When Only the Zero Resistor and Capacitor Are Adjustable

Introduction

As described in the references, a standard procedure can be used to determine the values of R₀, C₀, and C_P for a second-order loop filter in a phase-locked loop (PLL). It uses open-loop bandwidth (ω₀) and phase margin (ϕ_M) as design parameters, and can be extended to third-order loop filters to determine R₂ and C₂ (Figure 1). The procedure solves for C_P directly and subsequently derives the remaining values.

In some cases, C_P, R₂, and C₂ may be fixed-value components integrated within the PLL, leaving only R₀ and C₀ available for controlling the loop response. This nullifies the aforementioned procedure because C_P cannot be adjusted. This article proposes an alternative procedure that can be used when the value of C_P is fixed, and addresses limitations imposed by the inability to control the value of C_P.

Assumptions

This loop filter design method relies on two assumptions that are typically used in third-order passive filter designs that extend a second-order loop filter design to third-order by compensating for the presence of R₂ and C₂ through adjustment of R₀ and C₀.

1. The pole frequency resulting from R₂ and C₂ should be at least an order of magnitude greater than ω0 (the desired open-loop unity-gain bandwidth); specifically f₀ ≤ 0.1/(2πR₂C₂), where f₀ = ω₀/(2π).
2. The load of the series combination of R₂ and C₂ on the R₀-C₀-C_P network should be negligible.

Transfer Function of a Second-Order Loop Filter

A second-order loop filter has two time constants (T₁ and T₂) associated with its components:

The loop filter’s transfer function, in terms of T₁, T₂, and C_P, is important because it plays a significant role in the overall response of the PLL:

PLL System Function

The small signal model shown in Figure 2 provides the means for formulating the PLL response and a template for analyzing phase variation at the output resulting from a phase disturbance at the input. Note that the voltage-controlled oscillator (VCO), being a frequency source, behaves like an ideal phase integrator, so its gain (K_V) has a 1/s factor (the Laplace transform equivalent of integration). Hence, the small signal model of a PLL has frequency dependence (s = σ + jω).

The closed-loop transfer function (H_CL) for a PLL is defined as θ_OUT/θ_IN. The open-loop transfer function (H_OL), defined as θ_FB/θ_IN, is related to the closed-loop transfer function. It is instructive to express H_CL in terms of H_OL because the open-loop transfer function contains clues about closed-loop stability:

K represents the combined gains of the phase-frequency detector (PFD), charge pump, and VCO—that is, K = K_DK_V, where K_D is the charge pump current in amperes and K_V is the VCO gain in Hz/V. H_OL, H_CL, and H_LF are all functions of s. The negative sign in Equation 4 shows the phase inversion implied by the negative feedback to the summing node in Figure 2. Defining H_OL as in Equation 4 leads to subtraction in the denominator of Figure 5, which provides an intuitive explanation of closed-loop stability.

Inspection of Equation 5 reveals a potential loop stability problem. Given that H_OL is a function of complex frequency (s = σ + jω), it necessarily has frequency dependent magnitude and phase components. Therefore, if H_OL simultaneously exhibits unity gain and zero phase shift (or any integer multiple of 2π radians) for any particular value of s, the denominator of H_CL becomes zero, the closed-loop gain becomes undefined, and the system becomes completely unstable. This implies that stability is governed by the frequency-dependent magnitude and phase characteristics of H_OL. In fact, at the frequency for which the magnitude of H_OL is unity, the phase of H_OL must stay far enough from zero (or any integer multiple of 2π) to avoid a zero denominator in Equation 5.

The frequency, ω₀, at which the magnitude of H_OL is unity, holds great importance. The phase of H_OL at ω₀ defines the phase margin of the system ϕ_M. Both ω₀ and ϕ_M can be derived from H_OL.

Defining R₀ and C₀ in Terms of ω₀ and ϕ_M

Using the design parameters ω₀ and ϕ_M to determine the values of R₀ and C₀ requires expressions containing those four variables and other constant terms. Start with Equation 4, because it defines H_OL. This includes H_LF, which includes R₀ and C₀ via T₁ and T₂. Since H_OL has magnitude and phase, it stands to reason that ω₀ and ϕ_M can be incorporated as well.

Substituting Equation 3 into Equation 4 and rearranging terms yields Equation 6, which presents H_OL in terms of T₁ and T₂ along with constants K, N, and C_P:

Evaluation at s = jω, yields the frequency response of H_OL:

The (jω)² term in the denominator simplifies to –ω²:

The magnitude and phase of H_OL are:

Keep in mind that T₁ and T₂ are shorthand expressions for algebraic combinations of R₀, C₀, and C_P. Evaluating Equation 9 at ω = ω₀ and setting |H_OL| = 1 defines the unity gain frequency, ω₀, as the frequency at which the magnitude of H_OL is unity.

Similarly, evaluating Equation 10 at ω = ω₀ and setting ∠H_OL = ϕ_M defines the phase margin, ϕ_M, as the phase of H_OL at frequency ω₀ (the unity gain frequency).

It is a trivial matter to expand Equation 11 and Equation 12 by substituting Equation 1 for T₂ and Equation 2 for T₁, which brings R₀ and C₀ into the equations. Hence, we have succeeded in relating ω₀ and ϕ_M to the variables R₀ and C₀ along with constants K, N, and C_P.

Simultaneously solving the resulting equations for R₀ and C₀ is no trivial task. The symbolic processor available in MathCad^® can solve the two simultaneous equations, but arccos must be substituted for arctan. This transformation enables the symbolic processor to solve for R₀ and C₀, yielding the following solution sets (R_0A, C_0A; R_0B, C_0B; R_0C, C_0C; and R_0D, C_0D). See the Appendix for details on transforming Equation 12 to use the arccos function.

This result is problematic because the goal was to solve for R₀ and C₀ given ω₀ and ϕ_M, but this indicates four possible R₀, C₀ pairs instead of a unique R₀, C₀ pair. However, closer inspection of the four results leads to a single solution set as follows.

Note that in the context of modeling a PLL, all of the variables in the above equations possess positive values, including cos(ϕ_M) because ϕ_M is constrained to values between 0 and π/2. As a result, C_0A and R_0B are clearly negative quantities. Therefore, solution sets R_0A, C_0A and R_0B, C_0B are immediately ruled out because negative component values are not acceptable. The R_0C, C_0C and R_0D, C_0D results require further analysis, however.

Note that the four equations involving R_0C, C_0C and R_0D, C_0D possess the common factor:

Closer inspection reveals that Expression 13 has the form a² – (2ac)cos(β) + c². Equating this with the arbitrary quantity, b², yields:

Equation 14, the Law of Cosines, relates a, b, and c as the lengths of the three sides of a triangle with β being the interior angle of the vertex opposite side b. Since b² is the square of the length of one side of a triangle, it must be a positive quantity, which implies the right side of Equation 14 must also be positive. Thus, Expression 13 must be a positive quantity, which means the denominator of R_0D is positive. The numerator of R_0D is also positive, therefore R_0D must be negative, which rules out the R_0D, C_0D solution set. This leaves only the R_0C, C_0C pair as a contender for the simultaneous solution of Equation 11 and Equation 12.

Constraints on R₀ and C₀

Although Equation 15 and Equation 16 are contenders for the simultaneous solution of Equation 11 and Equation 12, they are only valid if they result in positive values for both R₀ and C₀. Close inspection of R₀ shows it to be positive—its numerator is positive, because the range of cos²(x) is 0 to 1—and its denominator is the same as Expression 13, which was previously shown to be positive. The numerator of C₀ is also the same as Expression 13, so C₀ is positive as long as its denominator satisfies the following condition:

This is depicted graphically in Figure 3, in which the left and right sides of Equation 17 are each equated to y (blue and green curves) with the horizontal axis sharing ω₀ and ϕ_M. The intersection of the two curves marks the boundary condition for ω₀ and ϕ_M. The condition under which Equation 17 is true appears as the red arc. The portion of the horizontal axis beneath the red arc defines the range of ϕ_M and ω₀ that ensures C₀ is positive. Note the point on the horizontal axis directly below the intersection of the blue and green curves establishes ϕ_{M_MAX}, the maximum value of ϕ_M to ensure C₀ is positive.

Equation 18 requires that C_PNω₀² be less than K in order to satisfy the constraints of the arccos function for ϕ_{M_MAX} between 0 and π/2. This establishes ω_{0_MAX}, the upper limit on ω₀ to ensure C₀ is positive.

Compensating for R₂ and C₂ (Third-Order Loop Filter)

In the case of a third-order loop filter, components R₂ and C₂ introduce additional phase shift, Δϕ, relative to the second-order loop filter:

To deal with this excess phase shift, subtract it from the desired value of ϕ_M:

Applying ϕ_{M_NEW} to Equation 15 and Equation 16 results in different values for R₀ and C₀ than for the second-order solution, with the new values compensating for the excess phase shift introduced by R₂ and C₂. The presence of R₂ and C₂ also affects ϕ_{M_MAX}, the maximum allowable value of ϕ_M. The new maximum value of ϕ_M (ϕ_{M_MAX_NEW}) is

Conclusion

This article demonstrates using open-loop unity-gain bandwidth (ω₀) and phase margin (ϕ_M) as design parameters for second-order or third-order loop filters when only components R₀ and C₀ are adjustable. Simulation of a PLL with a second-order loop filter using R₀ and C₀ yields an exact match to the theoretical frequency response of H_OL and the resulting phase margin, thereby validating the equations. The parameters ω₀ and ϕ_M have upper bounds for a second-order loop filter per Equation 19 and Equation 18, respectively.

The procedure for determining R₀ and C₀ assumed a second-order loop filter, but is extendible to third-order loop filter designs by adjusting the desired phase margin (ϕ_M) to a new value (ϕ_{M_NEW}) per Equation 21, yielding a new upper bound (ϕ_{M_MAX_NEW}) per Equation 22.

Although simulations using a second-order loop filter validated Equation 15 and Equation 16, validating the equations that extend the design procedure to third-order loop filter designs requires a redefinition of the loop filter response, H_LF(s), to include R₂ and C₂ as follows:

The incorporation of this form of H_LF into the H_OL and H_CL equations enables simulations of third-order loop filter designs using R₀ and C₀. Such simulations reveal the calculated values of R₀ and C₀ deviate from the theoretical frequency response and phase margin associated with H_OL for a PLL when using a third-order loop filter. This is predominantly due to the effect of R₂ and C₂ on H_OL in a third-order loop filter.

Recall that the formulas for R₀ and C₀ assume a second-order loop filter, but R₂ and C₂ do not exist in a second-order filter, so including them as part of the loop filter constitutes a source of error in spite of adjusting R₀ and C₀ to compensate for the phase shift introduced by R₂ and C₂. Even in the presence of this error, however, simulation indicates that using the adjusted values of R₀ and C₀, but limiting the choice of ω₀ to a maximum of ¼ of the value dictated by Equation 19 yields acceptable results. In fact, the simulated open-loop bandwidth and phase margin results deviate only slightly from the design parameters (ω₀ and ϕ_M) for a PLL using a third-order loop filter.

Simulation Results

The following is the result of running four simulations of a PLL with a third-order loop filter. The simulations all have the following fixed-loop filter components and PLL parameters:

C_P = 1.5 nF

R₂ = 165 kΩ

C₂ = 337 pF

K_D = 30 µA

K_V = 3072 (25 ppm/V at 122.88 MHz)

N = 100

Simulation 1 and Simulation 2 use ω₀ = 100 Hz, which is near the calculated upper limit of 124.8 Hz (ω_{0_MAX}). As such, Simulation 1 and Simulation 2 deviate from the design parameter values (ω₀ and ϕ_M) by nearly 10%. On the other hand, Simulation 3 and Simulation 4 use ω₀ = 35 Hz, which is approximately ¼ the upper limit. As expected, Simulation 3 and Simulation 4 hold much closer to the design parameters (ω₀ and ϕ_M), yielding an error of only about 1%.

Table 1 summarizes the simulation results and also includes the calculated values of R₀, C₀, ω_{0_MAX}, and ϕ_{M_MAX} for the given design parameters, ω₀ and ϕ_M. Note that for the purpose of comparison it would be preferable for both Simulation 1 and Simulation 3 to use ϕ_M = 80°, but Simulation 1 must satisfy the constraint imposed by Equation 22 of ϕ_M < 48° (hence the choice of 42°).

Table 1: Simulation Summary

Figure 4 and Figure 5 show the open- and closed-loop response for each simulation.

Appendix—Converting the Discontinuous Arctan Function to the Continuous Arccos Function

Equation 10 demonstrates that the angle ϕ is the difference between angle θ₂ and angle θ₁, where θ₂ = arctan(ωT₂) and θ1 = arctan(ωT₁). Furthermore, ωT₂ is expressible as x/1 and ωT₁ as y/1:

This implies the geometric relationship shown in Figure 6, with θ₁ and θ₂ defined by the triangles of Figure 6 (b) and (a), respectively. Figure 6 (c) combines these two triangles to show ϕ as the difference between θ₁ and θ₂.

The Law of Cosines relates an interior angle (θ) of a triangle to the lengths of the three sides of the triangle (a, b, and c) as follows:

Applying the Law of Cosines to angle ϕ in Figure 6 (c) yields:

Solving for ϕ:

But, x/1 = ωT₂ and y/1 = ωT₁, allowing ϕ to be expressed in terms of T₁ and T₂.

References

Brennan, Paul V. Phase-Locked Loops: Principles and Practice. McGraw-Hill, 1996.

Keese, William O. AN-1001, National Semiconductor Application Note, An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops. May 1996.

MT-086: Fundamentals of Phase Locked Loops (PLLs).

PLLs/PLLs with Integrated VCOs.

Author

Ken Gentile

Ken Gentile joined Analog Devices in 1998 as a system design engineer with the Clock and Signal Synthesis product line in Greensboro, NC, where he specializes in direct digital synthesis, analog filter design, and writing GUI-based engineering tools in MATLAB. Ken holds 10 patents. He has published 14 articles in various industry trade journals and over a dozen ADI application notes, as well as having presented at ADI’s annual General Technical Conference (GTC) in 2001, 2005, and 2006. He graduated with honors in 1996 with a B.S.E.E. from North Carolina State University. In his spare time, Ken enjoys reading, mathematical puzzles, and most anything related to science, engineering, and “backyard” astronomy.