MAX9384

The MAX9384 fully differential dual 2:1 multiplexer (mux) features extremely low propagation delay (560ps max) and output-to-output skew (40ps max). The device is ideal for clock and data multiplexing applications. The two 2:1 muxes are controlled individually or simultaneously through mux select inputs COM_SEL, SEL0, and SEL1. The mux select inputs are compatible with ECL/PECL logic, and are referenced to on-chip outputs V_BB0 and V_BB1, nominally V_CC - 1.33V.

The differential inputs D, D-bar can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip supply output V_BB as a reference voltage. All the differential inputs have bias and clamp circuits that force the outputs to a low default when the inputs are left open or at V_EE. The single-ended mux select inputs have pulldowns to V_EE, providing low default inputs when the select inputs are left open.

The device operates with a wide supply range (V_CC - V_EE) of +3.0V to +5.5V for PECL or -3.0V to -5.5V for ECL, and is pin compatible with the MC100LVEL56 and MC100EL56. The MAX9384 is offered in a 20-pin wide SO package, and is specified for operation from -40°C to +85°C.

Applications

• Access Multiplexers (DSLAM/DLC)
• Central Office Backplane Clock Distribution
• High-Speed Telecom and Datacom Applications