DS2153Q
E1 Single Chip Transceiver
Part Details
- Complete E1 (CEPT) PCM-30/ISDN-PRI transceiver
- LIU for clock/data recovery and waveshaping
- 32-bit or 128-bit jitter attenuator
- Generates line build-outs for both 120Ω and 75Ω lines
- Frames to FAS, CAS, and CRC4 formats
- Dual elastic buffers connect to backplanes up to 8.192MHz
- 8-bit parallel control port for muxed or nonmuxed buses
- Extracts/inserts CAS signals
- Detects/generates remote and AIS alarms
- Programmable output clocks for Fractional E1, H0, and H12
- Independent transmit and receive functions
- Full access to both Si and Sa bits
- Three separate testing loopbacks
- Counters for bipolar code, CRC4, and code FAS errors and Ebits
- Pin-compatible with DS2151Q T1 SCT
- Operating ranges:
- 5V, low-power CMOS
- 0°C to +70°C (DS2153Q)
- -40°C to +85°C (DS2153QN)
The DS2153Q is a first-generation line interface unit for E1 lines that pioneered single-chip integration of multiple functions combining long- and short-haul and framing functionality with dual elastic stores and an 8-bit parallel control port. It is pin- and function-compatible with the DS2151Q, its T1 counterpart. It continues to provide an adaptable, single-chip interface unit at both central office and local E1 network interfaces.
The DS2153Q meets all E1 specifications, including ITU G.703, G.704, G.706, G.823, and I.431 as well as ETSI 300 011, 300 233, TBR 12, and TBR 13. Under processor control, the user can access the 71 8-bit internal registers to configure the DS2153Q to suit the application.
Documentation
Data Sheet 1
Reliability Data 1
Design Note 1
Technical Articles 1
This is the most up-to-date revision of the Data Sheet.
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