Data Sheet Errata
Documentation Errata for ADSP-SC595/SC596/SC598 SHARC+ Processor Hardware Reference
Doc ID: DOC-1945
Change
Appendix A-183 does not show the explicit enumerations for the registers iterated with "n". Registers generally begin with n=0 and are iterated by 1. There is no SPU0_SECUREC[0] and the SPU0_SECUREC[n] should be listed as shown in the table below.
Memory Mapped Address | Register Name | Description | Reset Value |
---|---|---|---|
0x3108B980 | Reserved | Reserved | Reserved |
0x3108B984 | SPU0_SECUREC1 | SPU0 Secure Core Register 1 | 0x00000001 |
0x3108B988 | SPU0_SECUREC2 | SPU0 Secure Core Register 2 | 0x00000001 |
Last Update Date: Sep 9 2024