ADSP-SC570

PRODUCTION

Single-core SHARC+ (w/384KB L1), arm® Cortex-A5, 1MB Shared L2, 10/100 Ethernet, 176-LQFP

Part Models
6
1ku List Price
Starting From $16.47
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Part Details

  • Dual-enhanced SHARC+ high performance floating-point cores
    • Up to 500 MHz per SHARC+ core
    • Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache)
    • 32-bit, 40-bit, and 64-bit floating-point support
    • 32-bit fixed point
    • Byte, short word, word, long word addressed
  • arm® Cortex-A5 core
    • 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle
    • 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity
    • 256 kB L2 cache with parity
  • Powerful DMA system
  • On-chip memory protection
  • Integrated safety features
  • 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant
  • Low system power across automotive temperature range

Memory

  • Large on-chip L2 SRAM with ECC protection, up to 1 MB
  • One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices

Additional Features

  • Security and Protection
    • Cryptographic hardware accelerators
    • Fast secure boot with IP protection
    • Support for arm® TrustZone
  • Accelerators
    • FIR, IIR offload engines
  • Qualified for automotive applications
ADSP-SC570
Single-core SHARC+ (w/384KB L1), arm® Cortex-A5, 1MB Shared L2, 10/100 Ethernet, 176-LQFP
adsp-sc570 Functional Block Diagrm
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Documentation

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Software Resources

Middleware 2

  • Operating Systems and Middleware
  • Lightweight TCP/IP (lwIP) Stack

    OBSOLETE: The Lightweight TCP/IP (lwIP) Stack for CrossCore Embedded Studio is an implementation of this widely accepted TCP/IP stack for embedded platforms supporting most of the networking protocols in the TCP/IP suite.

    View Details

Tools & Simulations


Evaluation Kits

eval board
EMULATOR-ADSP

Low Cost ICE-1000 and High Performance ICE-2000 USB-based JTAG Emulators

Features and Benefits

  • JTAG/SWD support for Blackfin, Blackfin+, SHARC and multi-core SHARC+ with ARM
  • Plug-n-Play, USB 2.0 compliant
  • USB bus-powered device
  • Windows® 8.1, Window 7 compatible
  • Multiple processor I/O voltage support: 1.8V, 2.5V, and 3.3V
  • Multiprocessor support
  • JTAG/SWD clock operation of 5 MHz on the ICE-1000
  • JTAG/SWD clock operation up to 46 MHZ on the ICE-2000
  • Multi-colored LED for enhanced status indication
  • Software controlled target reset to support remote debug

Product Details

The Analog Devices ICE-1000 and ICE-2000 emulators facilitate the creation, test, and debug of advanced applications on Analog Devices Processors and DSPs. Working in tandem with the CrossCore® Embedded Studio development environment, these emulators provide state-of-the-art support for all JTAG-compliant Analog Devices processors.

New debug feature added for the ICE-1000/ICE-2000:


  • Coresight Serial Wire Debug (SWD) 

eval board
ADZS-SC573-EZLITE

ADSP-SC573 Evaluation Hardware for the ADSP-SC57x/ADSP-2157x SHARC Family (400-ball, 17x17mm BGA)

Features and Benefits

  • ADSP-SC573 400-pin 17x17mm BGA
  • 2Gb DDR3 Memory
  • 128 Mb SPI Flash
  • 2 x Ethernet (1x 10/100, 1x GigE)
  • ADAU1979 quad ADC
  • ADAU1962A 12 channel 24-bit DAC
  • ADAU1977 quad ADC with diagnostics
  • SPDIF in/out, optical & coax
  • UART
  • 2 CAN transceivers + RJ11 connectors
  • USB OTG
  • SD/MMC memory connector
  • HADC
  • EI3 Expansion Interface
  • CrossCore® Embedded Studio EZ-KIT license and ICE-1000 emulator

Product Details

The ADSP-SC573 processor is a member of the SHARC® family of products. The ADSP-SC573 processor is based on the SHARC+ dual-core and the arm® Cortex-A5TM core. The ADSP-SC573 SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices Super Harvard Architecture. These 32-bit/40- bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with their large onchip SRAM, multiple internal buses to eliminate I/O bottlenecks, and innovative digital audio interfaces (DAI). New enhancements to the SHARC+ core add cache enhancements, branch prediction, and other instruction set improvements—all while maintaining instruction set compatibility to previous SHARC products. The EZ-KIT ships with all of the necessary hardware to get you up and running and start the evaluation immediately

EMULATOR-ADSP
Low Cost ICE-1000 and High Performance ICE-2000 USB-based JTAG Emulators
EMULATOR-ADSP
ADZS-SC573-EZLITE
ADSP-SC573 Evaluation Hardware for the ADSP-SC57x/ADSP-2157x SHARC Family (400-ball, 17x17mm BGA)
ADZS-SC573-EZLITE-Angle ADZS-SC573-EZLITE-Top ADZS-SC573-EZLITE-Bottom ADZS-SC573-EZLITE-Kit

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