ADSP-BF518F16
ObsoleteBlackfin Embedded Processor w/ 16 Mbit Flash memory and IEEE-1588 support
Part Details
- Up to 400MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter
RISC-like register and instruction model for ease of programming and compiler-friendly support - Wide range of operating voltages
- Qualified for Automotive Applications
- 168-ball CSP_BGA or 176-lead LQFP_EP (with exposed pad)
- MEMORY
116K bytes of on-chip memory
External memory controller with glueless support for SDRAM and asynchronous 8-bit and 16-bit memories
Optional 16M bit SPI flash with boot option - PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588 support (ADSP-BF518/ADSP-BF518F16 only)
Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats - See datasheet for additional features
The ADSP-BF512, ADSP-BF514/ADSP-BF514F16, ADSP-BF516, ADSP-BF518/ADSP-BF518F16 processors are members of the Blackfin® family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
The ADSP-BF518F16 products have been introduced to replace the now obsolete ADSP-BF51xF products. The processors are completely code compatible with other Blackfin processors.
By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like programmability, multimedia support, and leading-edge signal processing in one integrated package.
PORTABLE LOW POWER ARCHITECTUREBlackfin processors provide world-class power management and performance. They are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. This capability can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This allows longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF51x processors are highly integrated system-on-achip
solutions for the next generation of embedded network
connected applications. By combining industry-standard interfaces
with a high performance signal processing core, costeffective
applications can be developed quickly, without the
need for costly external components. The system peripherals
include an IEEE-compliant 802.3 10/100 Ethernet MAC with
IEEE-1588 support (ADSP-BF518/ADSP-BF518F16 only), an
RSI controller, a TWI controller, two UART ports, two SPI
ports, two serial ports (SPORTs), nine general-purpose 32-bit
timers (eight with PWM capability), 3-phase PWM for motor
control, a real-time clock, a watchdog timer, and a parallel
peripheral interface (PPI).
BLACKFIN PROCESSOR CORE
As shown in Figure 2, the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.
The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. The compare/select and vector search instructions are also provided.
Documentation
User Guide 1
Application Note 44
Processor Manual 3
Software Manual 11
Emulator Manual 3
Evaluation Kits
Low Cost ICE-1000 and High Performance ICE-2000 USB-based JTAG Emulators