ADSP-2183
NOT RECOMMENDED FOR NEW DESIGNS16-bit, 52 MIPS, 3.3 v, 2 serial ports, host port, 80 KB RAM
Part Details
- 19 ns Instruction Cycle Time from 26.32 MHz Crystal @ 3.3 Volts
- 52 MIPS Sustained Performance
- 80K Bytes of On-Chip RAM, Configured as 16K Words On-Chip Program Memory RAM and 16K Words On-Chip Data Memory RAM
- Dual Purpose Program Memory for Both Instruction and Data Storage
- ADSP-2100 Family Code Compatible, with Instruction Set Extensions
- 16-Bit Internal DMA Port for High Speed Access to On-Chip Memory
- 4 MByte Memory Interface for Storage of Data Tables and Program Overlays
- 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers
The ADSP-2183 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.
The ADSP-2183 combines the ADSP-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory.
The ADSP-2183 integrates 80K bytes of on-chip memory configured as 16K words (24-bit) of program RAM, and 16K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. The ADSP-2183 is available in a 128-lead LQFP package.
In addition, the ADSP-2183 supports new instructions, which include bit manipulations-bit set, bit clear, bit toggle, bit test- new ALU constants, new multiplication instruction (x squared), biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking, for increased flexibility.
Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2183 operates with a 19 ns instruction cycle time. Every instruction can execute in a single processor cycle.
The ADSP-2183's flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle the ADSP-2183 can:
- generate the next program address
- fetch the next instruction
- perform one or two data moves
- update one or two data address pointers
- perform a computational operation
Documentation
Data Sheet 1
Application Note 64
Technical Articles 1
Processor Manual 4
Software Manual 5
Emulator Manual 1
Integrated Circuit Anomaly 1
Legacy Emulator Manual 1
This is the most up-to-date revision of the Data Sheet.
Software Resources
Code Examples 1
Software & Tools Anomaly 1
Evaluation Software 0
Tools & Simulations
Evaluation Kits
EZ-ICE® Serial Emulator for ADSP-218x Processor Family
EZ-KIT Lite Evaluation Kit for ADSP-218x Processor
Resources
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