ADSP-21061L

NOT RECOMMENDED FOR NEW DESIGNS

SHARC, 44MHz, 150 MFLOPS, 3.3v, floating point

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Part Details

  • 50MHz (20ns instruction rate) SISD SHARC Core
  • 150MFLOPs peak performance
  • Code compatible with all SHARC processors
  • Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math
  • 1Mbit of on-chip dual-ported SRAM
  • Glueless connection for scalable DSP multiprocessing
  • Two synchronous serial ports with independent transmit and receive functions
  • 6 Channel DMA controller
  • Host Processor Interface
ADSP-21061L
SHARC, 44MHz, 150 MFLOPS, 3.3v, floating point
ADSP-21061 Functional Block Diagram
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Documentation

Data Sheet 1

Application Note 38

Processor Manual 2

Integrated Circuit Anomaly 1

Legacy Emulator Manual 2

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Software Resources

Software & Tools Anomaly 1


Tools & Simulations

BSDL Model File 2

Designing with BGA

Surface Mount Assembly Recommendations for Plastic Ball Grid Array (PBGA) Packages

Open Tool

IBIS Model 1

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