AD15452

Obsolete

12-Bit 65 MSPS Quad A/D Converter with Integrated Signal Conditioning

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Part Details

12-Bit, 65 MSPS Quad Analog to Digital Converter
475 mW per Channel
Anti-Jam GPS Receivers
Differential Input with 100 Ω Input Impedance
Quad LVDS Output
Wireless and Wired Broadband Communications

Communications Test Equipment
Data Clock Output Provided
Full Scale Analog Input: 296 mVp-p
200 MHz 3 dB Bandwidth
Offset Binary Output Data Format
SNR@-9 dBfs: 64 dBfs (70 MHz Ain), 64 dBfs (140 MHz Ain)
SFDR@-9 dBfs: 81 dBfs(70 MHz Ain), 73 dBfs (140 MHz Ain)

Documentation

Application Note 5

AN-741: Little Known Characteristics of Phase Noise (Rev.0) 11/29/2004

AN-501: Aperture Uncertainty and ADC System Performance (Rev.A) 02/14/2015

AN-282: Fundamentals of Sampled Data Systems 02/14/2015

AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev.0) 02/14/2015

AN-835: Understanding High Speed ADC Testing and Evaluation 07/01/2020

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