LTC3617

推荐新设计使用

用于 DDR 终端的 ±6A、单片式、同步降压型稳压器

产品模型
4
产品技术资料帮助

ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许,也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。

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产品详情

  • ±6A 输出电流
  • 2.25V 至 5.5V 输入电压范围
  • ±10mV 输出电压准确度
  • 专为低至 0.5V 的低输出电压而优化
  • 高效率
  • 用于 VTTR = VDDQIN • 0.5 的集成型缓冲器
  • 停机电流:<1μA
  • 可调开关频率:高达 4MHz
  • 任选的内部补偿
  • 内部软起动
  • 电源良好状态输出
  • 输入过压保护
  • 耐热性能增强型 24 引脚 3mm x 5mm QFN 封装
LTC3617
用于 DDR 终端的 ±6A、单片式、同步降压型稳压器
Efficiency and Power Loss vs Load Current Product Package 1
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参考资料

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硬件生态系统

部分模型 产品周期 描述
硅振荡器 1
LTC6908 具扩频调制功能、采用电阻器设定频率的 SOT-23 封装振荡器
数字电源系统管理器 1
LTC2974 推荐新设计使用 具有精确输出电流的4通道PMBus电源系统管理器
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工具及仿真模型

LTspice

LTspice®是一款强大高效的免费仿真软件、原理图采集和波形观测器,为改善模拟电路的仿真提供增强功能和模型。


评估套件

eval board
DC1707A

LTC3617EUDD Demo Board | VIN=2.25V to 5.5V, VOUT1 = 0.5VIN (VTT) @ ±6A, VOUT2 = 0.5VIN (VTTR) @ ±10mA

产品详情

Demonstration circuit 1707 is a high efficiency monolithic step-down DC/DC switching regulator designed for double-data-rate (DDR) memory termination in computer systems. The VTT output is capable of sourcing and sinking up to 6A with an output voltage equal to one-half the voltage applied to the VDDQIN terminal or one-half the input supply voltage, selected by a jumper. An additional low current output (VTTR) also equal to one-half the voltage on VDDQIN can source and sink up to 10mA. Input voltage range is from 2.25V to 5.5V with overvoltage protection for transients exceeding 6.5V.


 


DC1707A
LTC3617EUDD Demo Board | VIN=2.25V to 5.5V, VOUT1 = 0.5VIN (VTT) @ ±6A, VOUT2 = 0.5VIN (VTTR) @ ±10mA
DC1707A - Schematic

参考电路

Artix US+ Rail Consolidation – Minimum Rails (AU10P/15P) Power Tree
Artix UltraScale+ 参考设计

用于AU10/15P和AU20/25P的最低供电轨——非硬件验证设计

特性和优点

  • Xilinx Artix® UltraScale+ devices are the industry’s only cost-optimized FPGAs based on an advanced, production-proven 16nm architecture for best-in-class performance/watt.

  • Analog Devices, Inc. supports power delivery solutions for the Artix Ultrascale+ low-cost designs. Monolithic solutions are used to power Xilinx FPGA and/or SoC rails as well as other system rails. These regulators are highly integrated discrete solutions optimized for cost, efficiency and footprint.

  • ADI provides supporting documentation including power schematics, layout, LTpowerPlanner® and applicable LTpowerPlay® configuration files to enable you to validate the power solution for your application seamlessly.

  • For a complete list power designs and use cases, please contact your local FAE.

  • Key Power for full management devices are used as follows:

    • LTC3307A
    • LTC3309A
    • ADP125
    • LTC3617 (Optional DDR)
    • LTC3618
    • ADM1186 (Optional Monitoring & Sequencing)
Versal HBM Diagram
Versal HBM Non-Hardware Verified Design 参考设计

特性和优点

  • The Versal HBM series features heterogeneous integration of fast memory, secure connectivity, and adaptive compute to eliminate processing and memory bottlenecks for memory-bound, compute-intensive workloads such as machine learning, database acceleration, next-generation firewalls, and advanced network testers. Analog Devices has worked closely AMD to develop verified power solutions that optimize cost, size and efficiency in high performance applications.
  • ADI provides supporting documentation including LTpowerPlanner and applicable LTpowerPlay configuration files to enable you to validate the power solution for your application seamlessly. For a complete list  power designs and use cases, please contact your local local FAE.
  • ADI has also completed a complete power evaluation report for Mid-High Voltage rails. For a complete report please submit your interest here.

Key power regulators are used for this device as follows:

  • LTC3888-1
  • LTC7051
  • LTC3633A
  • LTC7200S
  • LTC7151S
  • LT8652
  • ADP125
  • LTC3617 (Optional)
  • LTC3618 (Optional)
Artix UltraScale+
用于AU10/15P和AU20/25P的最低供电轨——非硬件验证设计
Artix US+ Rail Consolidation – Minimum Rails (AU10P/15P) Power Tree
Artix US+ Rail Consolidation - Minimum Rails (AU20P/25P) Power Tree
Versal HBM Non-Hardware Verified Design
Versal HBM Diagram

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