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  • Resource_types.lvl0:Technical Documentation > Frequently Asked Question
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  1. Can I input RGB Bayer pattern directly to the ADV202/212?
    Frequently Asked Question
    No. The ADV202/212 only accepts YCbCr 4:2:2 component format or single component format.
  2. How can JPEG2000 be used in home video distribution?
    Frequently Asked Question
    JPEG2000 Enables Wireless HD Video Distribution in the Home Download pdf
  3. What is the compression rate of the ADV202/ADV212?
    Frequently Asked Question
    The compression rate is not defined in the JPEG2000 ISO/IEC15444-1 standard which is implemented on the ADV202/212. Any compression rate can be programmed with the ADV202/212 encode parameters. The part can be configured to provide a fixed compression rate with a variance of +5% of the programmed value, down to -100% of the programmed value. The compression rate is programmed with the RCType and RCVal encode parameters [refer to Programming Guide].
  4. How to determine latency?
    Frequently Asked Question
    The ADV202's latency is generally 1.5 fields in encode or decode mode. If frames are input, the the latency is in frames. ADI does not provide exact specification of latency, since it depends on a lot of factors which would make an exact specification difficult. Complexity of input image, # of wavelet transform levels, choice of wavelet filters, choice of output format will all effect latency but nevertheless it will be kept in the …
  5. Are there any artifacts on tile boundaries after merging tiles?
    Frequently Asked Question
    Generally tiles can be merged on boundaries without artifacts. ADI provides a tile simulation software at: JPEG200 Eval Software Allows you to evaluate tile artifacts.
  6. Is the ADV202/212 output compatible with any JPEG2000 software codecs?
    Frequently Asked Question
    Yes. The ADV202/212 compressed output, if .j2c or jp2 format, is fully compatible to the ISO/IEC 15444-1 JPEG2000 standard. Note, the ADV202/212 will insert a 16-byte header at the start of each codestream. This header has to be removed in order for other JPEG2000 codecs to recognize the codestream correctly. Commonly used with the ADV202/212, Kakadu is a free of charge software codec from www.kakadusoftware.com
  7. What evaluation systems are available for the ADV202/212?
    Frequently Asked Question
    1. ADV202/212 ASD P160 EB is an ADV202/ADV212 daugther card designed for a Memec Xilinx Spartan 3SXLC motherboard. Input: analog NTSC or PAL in CVBS or S-Video format Output: analog NTSC or PAL in CVBS or S-Video format The boards can be used in a stand-alone application. In this case modes are controlled over DIP switches. In PC control mode access to registers, parameter settings is possible. The board is …
  8. What are Multilayers?
    Frequently Asked Question
    Multilayer codestream means, that the JPEG2000 output stream contains several layers of which each layer contains data compressed at a different compression ratio. The number of layers can be programmed with the ADV202/212. On the decoding side it is then possible to extract a particular layer only. The data has to be encoded in Multilayer mode. To do this, the JPEG2000 parameter RCTYPE is set to Multi-layered Target Size or Multi-layered Target …
  9. How to configure the ADV202/212 for 4Kx4K input images
    Frequently Asked Question
    If the image data is monochrome, It is required to tile the input into 16 1K x 1K tiles before compression and send them sequentially to the ADV202/212. Considering the HDATA data input rate limitations, this would allow an input rate of approx. 40 images/sec. For color images the images would have to be tiled further to stay under the maximum image size limit of 1.048 Msamples/image. A recommended configuration for …
  10. Can I input raw image data that comes from a high resolution still image source?
    Frequently Asked Question
    Yes. There are two methods to input raw image data to the ADV202: Over the VDATA bus using Raw Video Mode. This requires a synchronized pixel clock [Vclk] and HVF inputs along with the pixel data. HVF inputs are used in conjunction with the dimension register settings and define the image dimensions to be captured. Generally no horizontal or vertical blanking regions are expected with the input data. Refer to the ADV202/212 Programming Guide …
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Results on EngineerZone

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    1. IIO Absolute Time Tagging to GPSDO and PPS for SDR

      Forum Thread
      Answered
      Design Support AD9361/AD9363/AD9364
      20 June, 2025
      I need to have time accurate or time tagged I/Q data. Adding PPS and a GPSDO are straightforward enough to a reference design. Does there exist any concept of absolute time in IIO? Could I easily extended iio to support time tags? Utilities like iio_readdev seem to suggest …
      iioad9361sdrplutoWideband Transceiver ICRF Integrated Transceivers

    2. SIO (Set Output) command in TMCL

      Forum Thread
      Answered
      Other Products (EN)
      19 June, 2025
      I'm using the TMCM-3216-TMCL board with the TCML-IDE 4.7.1 and try to flip the digital IO pins using the SIO command. I can't see any voltage change on the output pin nor any change in the LED indicator on the board. Is there …
      hardwareTMCM-3216-TMCL

    3. phase difference in channels

      Forum Thread
      Answered
      High-Speed ADCs
      18 June, 2025
      Hello there, I used an AD9613 EVAL-BOARD for sampling from two sine signal (two sine signal with 0 phase difference that checked up with oscilloscope too) but when I use Matlab I see that there is 180 degrees phase difference between CH1 and Ch2 of AD9613. why there is …
      Datasheet/SpecsHigh Speed A/D Converters &gt;10 MSPSad9613Standard High Speed A/D Converters

    4. input noise of the EVAL-AD9248

      Forum Thread
      Answered
      High-Speed ADCs
      18 June, 2025
      Hi I want to know what the input noise of the EVAL-AD9248. Thanks
      hardwareEVAL-AD9248ad9248High Speed A/D Converters &gt;10 MSPSStandard High Speed A/D Converters

    5. AD8293G80 Figure 6 and (Figure 9).

      Forum Thread
      Answered
      Instrumentation Amplifiers
      18 June, 2025
      The data sheet indicates that the input common mode range extends to 0V. And the /reference input should be at least 0.8V above 0V and 0.8V below Vs+. But what does the pink area of Figure 6 mean in the datasheet? My input would be roughly -in = 0V …
      amplifiersInstrumentation Amplifiers

    6. CLOCK NOISE IS HIGH

      Forum Thread
      Answered
      Clock and Timing
      18 June, 2025
      Hi;We are building a tranceiver system and block diagram like following: where ADC's sampling rate is 500KHz and both AD9520's configuration are same except remote AD9520's ref divider is 5:Zero Delay: onVCO Divider: 2Phase Detector Frequency: 10MVCO Frequency:1600MCharge Pump Current: 1.8MALoop Bandwidth: 10kHzLoop …
      Clock Generation Devicesad9520-4Clock Generation and Distributionhardware

    7. Issues with serial input ports

      Forum Thread
      Answered
      SigmaDSP Processors & SigmaStudio Dev. Tool
      17 June, 2025
      Hi all,I'm having trouble getting the serial input ports other than the first one to work.This is my setup:Serial input port 0: it's connected to an ADC that acts as an I2S master.Serial input port 1: it's connected to a microcontroller that acts …
      Audio Signal Processorsadau1452adchardwaremcuserial inputi2sSigmaDSP Audio Processors

    8. Not reading data correctly.

      Forum Thread
      Answered
      High-Speed DACs
      17 June, 2025
      The output of the JESD204B interface is not always correct. Below are my settings for the JESD204B interface. CS = 0 Control bits per Sample N' = 16 total number of bits per Sample N = 16 Converter Resolution M = 2 Converters per device S = 1 Samples per Converter per Frame CF = 0 …
      hardwareHigh Speed D/A Converters =30MSPSMAX5871incorrect dataFast Precision D/A Converters

    9. Need help to troubleshoot the simulation.

      Forum Thread
      Answered
      LTspice
      17 June, 2025
      Hi Engineers, I'm in the middle of the preliminary design of a converter that uses a forward converter at the primary side and a full bridge converter at the secondary side. However, the efficiency keeps getting stuck and is not able to reach >80% as expected. Appreciate your help …
      software

    10. AD9576 Eval board SPI configuration support and frequency conversion with dual PLL

      Forum Thread
      Answered
      Clock and Timing
      17 June, 2025
      Hi Team, Here we are trying to configure AD9576 eval board. We need your support in configuring the SPI communication ( Pins in Eval board hardware and the setting to be used in ACE installer). Also can you please assist in, 1. To convert the on-board crystal Ref input 25MHz …
      Clock Generation and DistributionhardwareClock Distribution DevicesAD9576ACE installer

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