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Results on Analog.com

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  1. EVAL-AD917x
    Evaluation Board & Kit
    The AD9171, AD9172, and AD9173 evaluation boards are FMC form-factor boards with FMC connectors that comply to the Vita 57.1 standard. The FMC boards use a Mini-Circuits balun on the DAC output. To operate the evaluation board, the user must attach the board to a compatible FMC carrier board, such as those provided by FPGA vendors. Analog Devices produces an FPGA carrier called the ADS7-V2, which serves as a digital pattern …
    EVAL-AD917x

    Documentation

  2. EVAL-AD916X
    Evaluation Board & Kit
    This user guide is for the AD9161, AD9162, AD9163, and AD9164 evaluation board. The evaluation board connects to an ADS7-V2EBZ pattern generator for quick evaluation of the AD9161, AD9162, AD9163, and AD9164, high speed, RF digital-to-analog converters (RF DACs). The ADS7-V2EBZ automatically formats the data and sends it to the evaluation board, which simplifies evaluation of the device. The evaluation board runs from the FPGA mezzanine card (FMC) power supply. The …
    EVAL-AD916X

    Documentation

  3. EVAL-AD817X
    Evaluation Board & Kit
    The AD8175 and AD8176 are high speed, triple 16 × 9 video crosspoint switch matrixes with a gain of 2 and 4, respectively. Both the AD8175 and AD8176 support 1600 × 1200 RGB displays at a 85 Hz refresh rate. The AD8175 has a 500 MHz bandwidth, 1800 V/μs slew rate, −88 dB crosstalk, and −94 dB isolation (at 5 MHz). The AD8176 has a 450 MHz bandwidth, 1650 V/μs slew rate, −82 dB crosstalk …
    EVAL-AD817X

    Documentation

  4. EVAL-AD717x-AD411x Mbed Console Code
    Mbed Support
    EVAL-AD717x-AD411x Mbed Code
  5. EVAL-AD910x Program Files
    Code Examples
    Mbed codes examples for AD9102 and AD9106 TxDAC and waveform generator, a high performance digital-to-analog converter (DAC) integrating on-chip pattern memory for complex waveform generation with a direct digital synthesizer (DDS).
  6. EVAL-AD717x-AD411x-IIO Code
    Mbed Support
    IIO firmware for the AD717x and AD411x family of devices.
  7. EVAL-AD717x-AD411x-IIO Code
    Mbed Support
  8. 046277 Design Files
    Evaluation Design File
    The 046277 Design Files for the EVAL-AD916X Evaluation Board contain Layout, BOM, and schematic.

    ZIP

    18.46 M

  9. 046215 Design Files
    Evaluation Design File
    The 046215 Design Files for the EVAL-AD916X Evaluation Board contain Layout, BOM, and schematic.

    ZIP

    11.65 M

  10. AD9776A/AD9778A/AD9779A Software and Documentation Update
    Evaluation Software

Results on EngineerZone

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    1. EVAL-AD917x with external clock at 10 MHz

      Forum Thread
      Answered
      High-Speed DACs
      11 October, 2023
      … PLL1 Ref Clock" and returns an error saying that I should be an integer multiple or fraction of 122.88 MHz.Has anyone had success clocking the EVAL-AD917x with a frequency that is not an integer multiple or fraction of 122.88 MHz, without replacing the VCXO? Thank you.
      Clock Generation DevicesStandard High Speed D/A ConvertersClock Generation and Distributionhmc7044EVAL-AD9174clock and timingHigh Speed D/A Converters =30MSPSAD9174-FMC-EBZexternal referenceexternal clock

    2. Mechanical Model for EVAL-AD917x

      Forum Thread
      Answered
      High-Speed DACs
      01 April, 2022
      I am looking for a mechanical model of the EVAL-AD917x eval board. Do you have any mechanical drawings or models readily available? (STEP, or PDF drawings) Thanks for the help in advance. - Jonathan
      AD917X

    3. ADS8-V1EBZ ，AD9208-3000EBZ And EVAL-AD917x HDL Project

      Forum Thread
      Answered
      High-Speed ADCs
      10 September, 2021
      Hello, ADI:I am using ADS8-V1EBZ and AD9208-3000EBZ and EVAL-AD917x (9172) development boards.Is ADI willing to provide open source HDL projects for FPGA secondary development? We want to integrate three circuit boards into one circuit board.
      ADS8-V1EBZad9208-3000ebz

    4. EVAL-AD917x iio support

      Forum Thread
      Answered
      Linux Software Drivers
      9/6/2024 7:37:56 AM
      Is there IIO support for the EVAL-AD917x board ? If I were to get one of the zcu102 boards, is it possible to install the adi kernel + iio HDL bitstreams and test this evaluation board ? If so, then is it possible to list any links to the repos/information ? thanks …
      AD9176xilinxiioStandard High Speed D/A ConverterssoftwareHigh Speed D/A Converters =30MSPSEVAL-AD917xlinuxdac

    5. RE: ADS8-V1EBZ ，AD9208-3000EBZ And EVAL-AD917x HDL Project

      Forum Reply
      High-Speed ADCs
      23 September, 2024
      Assume answered offline.

    6. RE: EVAL-AD917x iio support

      Forum Reply
      Linux Software Drivers
      9/11/2024 2:22:48 AM
      Please see here: https://wiki.analog.com/resources/tools-software/linux-software/kuiper-linux/project-list EVAL-AD9172 and similar are supported by our Kuiper SD card image. https://wiki.analog.com/resources/tools-software/linux-software/kuiper-linux/project-list The kernel and HDL bitstream is completely build from …

    7. RE: EVAL-AD917x with external clock at 10 MHz

      Forum Reply
      High-Speed DACs
      06 November, 2023
      Glad to hear it! If you can mark this question as answered we can close it on our end. Best regards.

    8. RE: EVAL-AD917x with external clock at 10 MHz

      Forum Reply
      High-Speed DACs
      06 November, 2023
      I've now received the eval board and tested your suggested approach. I can confirm that the PLL can lock to a 10 MHz reference when using the values shown in your screenshot, except for register set to instead of . Thank again!

    9. RE: EVAL-AD917x with external clock at 10 MHz

      Forum Reply
      High-Speed DACs
      25 October, 2023
      I'm glad to hear that you were able to make it work. I do not have an eval board to test this yet, but after taking another look at the datasheet of the HMC it seems like what you are observing makes sense. The LOS detection circuit is not …

    10. RE: EVAL-AD917x with external clock at 10 MHz

      Forum Reply
      High-Speed DACs
      24 October, 2023
      Hello, It looks like the lock issue is not due to the R1/N1 dividers, but rather the OSCIN and CLKIN1 prescalers. These two scaled signals are compared at the LOS circuit; currently OSCIN/4 is about 3x as fast as CLKIN1/1, so the LOS detect circuitry goes 3 …