ADRF6510
Obsolete30 MHz Dual Programmable Filters and Variable Gain Amplifiers
Part Details
- Matched pair of programmable filters and VGAs
- Continuous gain control range: −5 dB to +45 dB
- 6-pole filter
- 1 MHz to 30 MHz in 1 MHz steps, 0.5 dB corner frequency
- SPI programmable
- 6 dB front-end gain step
- IMD3: >55 dBc for 1.5 V p-p composite output
- HD2, HD3: >60 dBc for 1.5 V p-p output
- Differential input and output
- Adjustable output common-mode voltage
- Optional dc output offset correction
- Power-down feature
- Single 5 V supply operation
The ADRF6510 is a matched pair of fully differential low noise and low distortion programmable filters and variable gain amplifiers (VGAs). Each channel is capable of rejecting large out-of-band interferers while reliably boosting the wanted signal, thus reducing the bandwidth and resolution requirements on the analog-to-digital converters (ADCs). The excellent matching between channels and their high spurious-free dynamic range over all gain and bandwidth settings make the ADRF6510 ideal for quadrature-based (IQ) communication systems with dense constellations, multiple carriers, and nearby interferers.
The filters provide a six-pole Butterworth response with 0.5 dB corner frequencies programmable through the SPI port from 1 MHz to 30 MHz in 1 MHz steps. The preamplifier that precedes the filters offers a pin-programmable option of either 6 dB or 12 dB of gain. The preamplifier sets a differential input impedance of 400 Ω and has a common-mode voltage that defaults to 2.1 V but can be driven from 1.5 V to 2.5 V.
The variable gain amplifiers that follow the filters provide 50 dB of continuous gain control with a slope of 30 mV/dB. The output buffers provide a differential output impedance of 20 Ω that is capable of driving 1.5 V p-p into 1 kΩ loads. The output common-mode voltage defaults to VPS/2, but it can be programmed via the VOCM pin. The built-in dc offset correction loop can be disabled if dc-coupled operation is desired. The high-pass corner frequency is defined by external capacitors on the OFS1 and OFS2 pins.
The ADRF6510 operates from a 4.75 V to 5.25 V supply and consumes a maximum supply current of 258 mA when programmed to the highest bandwidth setting. When disabled, it consumes 2 mA. The ADRF6510 is fabricated in an advanced silicon-germanium BiCMOS process and is available in a 32-lead, exposed paddle LFCSP. Performance is specified over the −40°C to +85°C temperature range.
Applications
- Baseband I/Q receivers
- Diversity receivers
- ADC drivers
Documentation
Data Sheet 1
Application Note 1
Evaluation Design File 1
Circuit Note 2
Product Selection Guide 1
This is the most up-to-date revision of the Data Sheet.
Software Resources
Tools & Simulations
ADIsimRF
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
Open ToolADIsimPLL™
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
Open ToolEvaluation Kits
ADRF6510 Evaluation Board
Resources
Software
Reference Designs
An IQ Demodulator-Based IF-to-Baseband Receiver with IF and Baseband Variable Gain and Programmable Baseband Filtering, and Dual ADC