AD9625

RECOMMENDED FOR NEW DESIGNS

12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter

Data Sheet (Rev. C) Product Selection Table
Part Models
10
1ku List Price
Starting From $735.34
Viewing:

Part Details

  • 12-bit 2.5 GSPS ADC, no missing codes
  • SFDR = 79 dBc, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
  • SFDR = 77 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
  • SNR = 57.6 dBFS, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS
  • SNR = 57 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS
  • Noise spectral density = −149.5 dBFS/Hz at 2.5 GSPS
  • Differential analog input: 1.2 V P-P
  • Differential clock input
  • 3.2 GHz analog input bandwidth, full power
  • High speed 6- or 8-lane JESD204B serial output Subclass 1: 6.50 Gbps at 2.6 GSPS
  • Two independent decimate by 8 or decimate by 16 filters with 10-bit NCOs
  • Supply voltages: 1.3 V, 2.5 V
    • Flexible digital output modes
    • Built-in selectable digital test patterns
  • Timestamp feature
  • Conversion error rate < 10−15
AD9625
12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter
AD9625 Functional Block Diagram AD9625 Pin Configuration
Add to myAnalog

Add product to the Products section of myAnalog (to receive notifications), to an existing project or to a new project.

Create New Project
Ask a Question

Documentation

Data Sheet 1

User Guide 1

Technical Articles 15

Informational 1

Learn More
Add to myAnalog

Add product to the Products section of myAnalog (to receive notifications), to an existing project or to a new project.

Create New Project

Software Resources

Device Drivers 2

Hardware Ecosystem

Parts Product Life Cycle Description
Clock Distribution Devices 3
LTC6955
LAST TIME BUY Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family
LTC6953
LAST TIME BUY Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support
HMC7043
RECOMMENDED FOR NEW DESIGNS

High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C
Clock Generation Devices 3
HMC7044
RECOMMENDED FOR NEW DESIGNS High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support
LTC6952
LAST TIME BUY Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support
LTC6951
LAST TIME BUY Ultralow Jitter Multi-Output Clock Synthesizer with Integrated VCO
Digital Control VGAs 2
ADA4961
RECOMMENDED FOR NEW DESIGNS Low Distortion, 3.2 GHz, RF DGA
ADL5205
RECOMMENDED FOR NEW DESIGNS

Dual, 35 dB Range, 1 dB Step Size DGA
Fully Differential Amplifiers 3
ADL5569
RECOMMENDED FOR NEW DESIGNS 6.5 GHz, Ultrahigh Dynamic Range, Differential Amplifier
ADL5567
RECOMMENDED FOR NEW DESIGNS 4.3 GHz, Ultrahigh Dynamic Range, Dual Differential Amplifier
ADL5566
RECOMMENDED FOR NEW DESIGNS 4.5 GHz Ultrahigh Dynamic Range, Dual Differential Amplifier
Modal heading
Add to myAnalog

Add product to the Products section of myAnalog (to receive notifications), to an existing project or to a new project.

Create New Project

Tools & Simulations

Virtual Eval - BETA

Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.

Open Tool

AD9625 AMI Model

Open Tool

ADC Companion Transport Layer RTL Code Generator Tool

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

Open Tool

Visual Analog

For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.

Open Tool

ADIsimRF

ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.

Open Tool

AD9625 MATLAB ADIsimADC

Open Tool

Evaluation Kits

eval board
schematic 1
schematic 2
schematic 3
AD-FMCADC2-EBZ

AD9625 Evaluation and Synchronization

Buy Now View Details

Features and Benefits

  • 2.5 GSPS utilizing JESD204B high speed serial interface
  • Optional on-board or external clocking
  • Specific design and I/O added for multi-board synchronization

Product Details

The AD-FMCADC2-EBZ is a high-speed data acquisition board featuring the AD9625 single channel ADC at 2500 MSPS, in a FMC form factor which supports the JESD204B high speed serial interface. The AD9625 is a 12-bit monolithic sampling analog-to-digital converter (ADC) that operates at conversion rates of up to 2.5 GSPS. This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/anti-jamming measures.

The board meets most of the FMC specifications in terms of mechanical size, mounting hole locations, and more. Although this board does meet most of the FMC specifications, it’s not meant as a commercial off-the-shelf (COTS) board. If you want a commercial, ready to integrate product, please refer to one of the many FMC manufacturers and the FMC specification (ANSI/VITA 57.1).

This board is targeted to use the ADI reference designs that work with Xilinx development systems. ADI provides complete source (HDL and software) to re-create those projects (minus the IP provided by the FPGA vendors, which we use), but may not provide enough info to port this to your custom platform

The design of the board is specifically tailored to synchronizing multiple AD-FMCADC2-EBZ boards together.  For more information on synchronization please refer to A Test Method for Synchronizing Multiple GSPS Converters.

The reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM. It allows programming the device and monitoring its internal registers via SPI.

eval board
schematic 4
schematic 5
schematic 6
schematic 7
AD-FMCOMMS11-EBZ

Direct RF to Baseband Transmit Radio

Buy Now View Details

Features and Benefits

  • TX
    • 16-bit 12GSPS RFDAC
    • JESD204B Interface
      • 8 lanes up to 12.5Gbps
    • 1x/2x/4x/6x/8x/12x/16x/24x/32x Interpolation
    • 64-bit NCO at max rate
    • Analog Modes of Operation:
      • Normal Mode: 6GSPS DAC rate
        • Synthesis up to 2.5GHz (1st Nyquist)
      • Mix Mode: 6GSPS DAC rate
        • Synthesis in 2nd & 3rd Nyquist zones
      • 2X Normal Mode: 12GSPS DAC rate
        • Synthesis up to 6GHz (1st Nyquist)
      • Excellent dynamic performance
  • RX
    • 3.2GHz full power bandwidth at 2.5GSPS
      • Noise Density = -149.5dBFs/Hz, ENOB = 9.5 bits
      • SFDR = 77 dBc at 1GHz Ain (2.5Gsps)
      • SFDR = 77dBc at 1.8GHz Ain (2.5Gsps)
    • +/-0.3 LSB DNL, +/-1.0 LSB INL
    • Dual supplies : 1.3V and 2.5V
    • 8 or 6 Lane JESD204B Outputs
    • Programmable clipping threshold for Fast Detect output
    • Two Integrated wide band digital down converters (DDC) per channel
      • 10-bit complex NCO
      • 2 cascaded half band filters (dec/8, dec/16)
    • Timestamp for synchronous processing alignment
      • SYSREF Setup/Hold detector
    • Programmable Interrupt (IRQ) event monitor

Product Details

The AD-FMComms11-EBZ board is a system platform board for communication infrastructure applications that demonstrates the Direct to RF (DRF) transmitter and observation receiver architecture. Using high sample rate RFDAC(s) and RFADC(s), a number of components in previous generation transmitters can be eliminated, such as mixers, modulators, IF amplifiers and filters. The objective being to bring the ADC or DAC as close to the antenna as possible, leading to possibly more cost effective and efficient communications solution.

It is composed of multi-GSPS RF ADC and DAC, AD9625 and AD9162 respectively. The transmit path contains a balun, low pass filter, gain block and variable attenuation to produce an output appropriate for a power amplifier module. Along the observation path, the PA output is coupled back into the board through a variable attenuator, a balun and finally the ADC. Clock management is taken care of on board; all the necessary clocks are generated from a reference. Power management is present as well.

eval board
schematic 8
schematic 9
schematic 10
schematic 11
EVAL-AD9625

AD9625 Evaluation Board

Buy Now View Details

Product Details

Equipment Needed

  • AC to 12V DC power supplies (2)
  • Analog signal source, anti-aliasing filter and SMA cable
  • Clock source and SMA cable
  • PC running Windows
  • USB 2.0 cable
  • AD9625 Evaluation Board
  • HSC-ADC-EVALEZ FPGA Based Data Capture Board

Helpful Documents

  • AD9625 Datasheet
  • VisualAnalog Converter Evaluation Tool User Manual, AN-905
  • High Speed ADC SPIController Software User Manual, AN-878
  • Interfacing to High Speed ADCs via SPI, AN-877

Software Needed

  • VisualAnalog
  • SPIController

Analog Option

  • Single-Ended to Differential Balun input to AD9625

All documents and software are available at http://www.analog.com/fifo.

For any questions please send an email to highspeed.converters@analog.com.

eval board
schematic 12
schematic 13
AD-FMCADC3-EBZ

ADA4961 & AD9625 Analog Signal Chain Evaluation and Converter Synchronization

Buy Now View Details

Features and Benefits

  • 2.5 GSPS utilizing JESD204B high speed serial interface
  • Driver amplifier interface with 21dB voltage gain adjustment
  • Optional on-board or external clocking
  • Specific design and I/O added for multi-board synchronization

Product Details

The AD-FMCADC3-EBZ is a high speed data acquisition board featuring AD9625 single channel ADC at 2500 MSPS and the ADA4961 Low Distortion, 3.2 GHz, RF DGA driving the converter. The FMC form factor supports the JESD204B high speed serial interface. This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/anti-jamming measures.

The board meets most of the FMC specifications in terms of mechanical size, mounting hole locations, and more. Although this board does meet most of the FMC specifications, it’s not meant as a commercial off the shelf (COTS) board. If you want a commercial, ready to integrate product, please refer to one of the many FMC manufacturers and the FMC specification (ANSI/VITA 57.1). This board is targeted to use the ADI reference designs that work with Xilinx development systems. ADI provides complete source (HDL and software) to re-create those projects (minus the IP provided by the FPGA vendors, which we use), but may not provide enough info to port this to your custom platform.

The design of the board is specifically tailored to synchronizing multiple AD-FMCADC3-EBZ boards together. For more information on synchronization please refer to A Test Method for Synchronizing Multiple GSPS Converters.

The reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM. It allows programming the device and monitoring it’s internal registers via SPI.

eval board
schematic 14
schematic 15
schematic 16
AD-FMCADC7-EBZ

ADL5567 & AD9625 Analog Signal Chain Evaluation and ADF4355-2 Wideband Synthesizer with VCO

Buy Now View Details

Features and Benefits

  • Single channel of 2.5 GSPS conversion utilizing JESD204B high speed serial interface
  • Driver amplifier interface with 20dB voltage gain adjustment
  • On-board PLL and VCO setup for clocking or external clocking
  • True DC coupled input and analog input frontend to the ADC, BW = DC to 1.8GHz

    • Product Details

    The AD-FMCADC7-EBZ is a single channel high speed data acquisition board featuring the AD9625 12bit, ADC sampling at 2500 MSPS and a ADL5567 low distortion, 4.8 GHz, differential amplifier driving the converter. The FMC form factor supports the JESD204B high speed serial interface. All clocking is supported using the on-board ADF4355-2 wideband PLL with VCO. This product is designed for sampling wide bandwidth analog signals from DC to 1.8GHz. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications.


    The board meets most of the FMC specifications in terms of mechanical size, mounting hole locations, and more. Although this board does meet most of the FMC specifications, it’s not meant as a commercial off the shelf (COTS) board. If you want a commercial, ready to integrate product, please refer to one of the many FMC manufacturers and the FMC specification (ANSI/VITA 57.1).


    This board is targeted to use the ADI reference designs that work with Xilinx development systems. ADI provides complete source (HDL and software) to re-create those projects (minus the IP provided by the FPGA vendors, which we use), but may not provide enough info to port this to your custom platform.


    The design of the board is specifically tailored to allow for true DC coupling on the analog input of the amplifier throughout the signal chain to the converter. Yielding the widest spectrum possible for the AD-FMCADC7-EBZ.


    The reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM. It allows programming the device and monitoring it’s internal registers via SPI.

    eval board
    schematic 17
    schematic 18
    AD-FMCADC5-EBZ

    2 AD9625 ADC’s running at 2.5GSPS with an effective sampling rate of 5GSPS

    Buy Now View Details

    Features and Benefits

    • 2 AD9625 ADC’s interleaved to double sampling rate (shown at 5GSPS)
    • Double FMC wide board requiring two fully populated (transceivers mainly) FMC connectors on the carrier board
    • Includes reference designs to work with commonly available Altera and Xilinx development boards.

    Product Details

    The AD-FMCADC5-EBZ is a high speed single channel data acquisition board featuring two AD9625 ADCs. The board is provisioned to sample the single input at an effective sampling rate of 5GSPS, with both the ADCs running at 2.5GHz and sampling at both edges (the clocks are 180 out of phase to each other).

    Although this board does meet most of the FMC specifications, it is not meant as a commercial off the shelf (COTS) board. If a commercial, ready to go integrate product is required, please refer to one of the many FMC manufacturers.

    ADI also provides reference designs (HDL and software) for this board to work with commonly available Altera and Xilinx development boards.
    AD-FMCADC2-EBZ
    AD9625 Evaluation and Synchronization
    AD-FMCADC2-EBZ Eval Board AD-FMCADC2-EBZ Eval Board AD-FMCADC2-EBZ Eval Board
    AD-FMCOMMS11-EBZ
    Direct RF to Baseband Transmit Radio
    AD-FMCOMMS11-EBZ Block Diagram AD-FMCOMMS11-EBZ Evaluation Board AD-FMCOMMS11-EBZ Evaluation Board - Top View AD-FMCOMMS11-EBZ Evaluation Board - Bottom View
    EVAL-AD9625
    AD9625 Evaluation Board
    AD9625 Evaluation Board AD9625 Evaluation Board AD9625 Evaluation Board AD9625 Evaluation Board
    AD-FMCADC3-EBZ
    ADA4961 & AD9625 Analog Signal Chain Evaluation and Converter Synchronization
    AD-FMCADC3-EBZ_Front AD-FMCADC3-EBZ_Back
    AD-FMCADC7-EBZ
    ADL5567 & AD9625 Analog Signal Chain Evaluation and ADF4355-2 Wideband Synthesizer with VCO
    AD-FMCADC7-Front AD-FMCADC7-Back AD-FMCADC7-Combined
    AD-FMCADC5-EBZ
    2 AD9625 ADC’s running at 2.5GSPS with an effective sampling rate of 5GSPS
    AD-FMCADC5 Block Diagram AD-FMCADC5-EBZ front view

    Latest Discussions

    9 Weeks Ago
    RE: how to capture visual analog FFT data using matlab
    9 Weeks Ago
    RE: how much data can be captured in 1 sec
    View related discussion on EngineerZone®

    Recently Viewed