ADSP-21065L

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Low-Cost SHARC, 66 MHz, 198 MFLOPS, 3.3v, Floating Point

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2
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Part Details

  • 198 MFLOPS (32-bit floating-point)
  • 16K 32-bit Dual-ported on-chip memory (544 KBits configurable)
  • 64M x 32-bit word external address space
  • Glueless SDRAM interface
  • I2S mode supports up to 8 channels
  • 2 serial transmit/receive ports support 32-channel TDM
  • Two timers with event capture and PWM options
  • 12 programmable I/O pins
  • 10 DMA channels
  • Glueless multiprocessing with 2 ADSP-21065Ls
ADSP-21065L supports defense and aerospace applications (AQEC standard)
  • Download ADSP-21065L-EP data sheet (pdf)
  • Extended temperature range –55°C to +110°C
  • Controlled manufacturing baseline
  • One package assembly/test site
  • One wafer fabrication site
  • Enhanced product change notification
  • Qualification data available upon request
  • V62/13601 DSCC Drawing Number
ADSP-21065L
Low-Cost SHARC, 66 MHz, 198 MFLOPS, 3.3v, Floating Point
ADSP-21065 Functional Block Diagram
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Documentation

Data Sheet 1

User Guide 1

Application Note 48

Processor Manual 4

Product Highlight 3

Integrated Circuit Anomaly 1

Legacy Emulator Manual 2

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Software Resources

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Tools & Simulations

IBIS Model 1

BSDL Model File 2

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