CN0185

A block diagram of the circuit is shown in Figure 1. The analog input is sampled at 10 MSPS by the AD7400A Σ-Δ modulator. The 22 Ω resistors and 0.1 μF capacitor form a differential input noise reduction filter with a cutoff frequency of 145 kHz. The output of the AD7400A is an isolated 1-bit data stream. The quantization noise is shaped by a second-order Σ-Δ modulator, which shifts the noise to the higher frequencies (see the MT-022 Tutorial).

To reconstruct the analog input signal, follow the data stream by an ADG849 switch connected to a 3 V ADR443 reference to stabilize the peak-to-peak output of the MDAT.

The signal is then filtered by an active filter whose order is higher than the order of the modulator. A fourth-order Chebyshev filter is used for better noise attenuation. Compared to other filter responses (Butterworth or Bessel), the response of the Chebyshev provides the steepest roll-off for a given filter order. The filter is implemented using the dual AD8646, a rail-to-rail, input and output, low noise, single-supply op amp.

The ADuM5000 is an isolated dc-to-dc converter based on Analog Devices, Inc., iCoupler^® technology. It is used for the power supply to the isolated side of the circuit containing the AD7400A. The isoPower^® technology of the ADuM5000 uses high frequency switching elements to transfer power through a chip-scale transformer.

The circuit must be constructed on a multilayer printed circuit board (PCB) with a large area ground plane. Proper layout, grounding, and decoupling techniques must be used to achieve optimum performance (see the MT-031 Tutorial, Grounding Data Converters and Solving the Mystery of "AGND" and "DGND," the MT-101 Tutorial, Decoupling Techniques, and the ADuC7060/ADuC7061 evaluation board layout). Ensure that the PCB layout meets the emissions standards and isolation requirements between the two isolated sides (see the AN-0971 Application Note).

In order not to overdrive the AD8646, the input signal must be lower than the power supply (5 V). The output of the AD7400A is a stream of 1s and 0s with an amplitude equal to the AD7400A V_DD2 supply voltage. Therefore, the V_DD2 digital supply is 3.3 V supplied by the ADP121 linear regulator. Alternatively, if a 5 V supply is used for V_DD2, attenuate the digital output signal before connecting to the active filter. In either case, well regulate the supply because the final analog output is directly proportional to V_DD2.

The 5 V supply for the circuit in Figure 1 is supplied from an ADP3301 5 V linear regulator, which accepts an input voltage of 5.5 V to 12 V.

Analog Active Filter Design

The cutoff frequency of the low-pass filter mostly depends on the desired bandwidth of the circuit. There is a trade-off between the cutoff frequency and noise performance, and there is more noise if the cutoff frequency of the filter increases. This is especially true in this design because the Σ-Δ modulator shapes the noise and moves a large portion into the higher frequencies. The cutoff frequency in this design is 100 kHz.

For a given cutoff frequency, the smaller the transition band of the filter is, the smaller the noise is that passes through the filter. Of all the filter responses (Butterworth, Chebyshev, Bessel, and so on), the Chebyshev filter was chosen for this design because it has a smaller transition band for a given filter order. However, this smaller transition band comes at the expense of a slightly worse transient response.

The fourth-order filter is made up of two second-order filters, with a Sallen-Key structure. The Analog Filter Wizard and the NI Multisim were used to design the filter. The parameters used include the following:

• Filter type = low-pass, Chebyshev, 0.01 dB ripple
• Order = 4
• f_C = 100 kHz, Sallen-Key (updated format for clarity)

The recommended values generated by the program were used with the exception of the feedback resistors, which were reduced to 22 Ω.

Measurements

The circuit has a gain of 4.6875 and an output offset voltage of 1.5 V. A differential signal of 0 V results in a digital bit stream of 1s and 0s, where each occurs 50% of the time. The ADR443 output is 3.0 V; therefore, after filtering, there is a 1.5 V dc offset. A differential input of 320 mV ideally results in a stream of all 1s, which after filtering, yields a 3.0 V DC output. Therefore, the effective gain of the circuit is

GAIN = (3.0 − 1.5)/0.32 = 4.6875

From the measurements, the actual measured offset is 1.504V , and the gain is 4.69. The dc transfer function of the system is shown in Figure 2. Linearity was measured as 0.0465%.

Figure 3 shows the output voltage with no dc offset voltage vs. the input frequency. The input signal voltage is 40 mV p-p, which causes an output signal of 40 × 4.6875= 190 mV p-p. Note that there is approximately 10 mV of peaking in the frequency response function, corresponding to about 0.42 dB.

The system has good noise performance, with a noise density of 2.50 μV/√Hz at 1 kHz and 1.52 μV/√Hz at 10 kHz.

A complete design support package for this circuit note can be found at www.analog.com/CN0185-DesignSupport.