AD9262
NOT RECOMMENDED FOR NEW DESIGNS16-Bit, 2.5 MHz/5 MHz/10 MHz, 30 MSPS to 160 MSPS Dual Continuous Time Sigma-Delta ADC
- Part Models
- 6
- 1ku List Price
- Starting From $38.52
Part Details
- SNR: 83 dB (85 dBFS) to 10 MHz input
- SFDR: 87 dBc to 10 MHz input
- Noise figure: 15 dB
- Input impedance: 1 kΩ
- Power: 600 mW
- 1.8 V analog supply operation
- 1.8 V to 3.3 V output supply
- Selectable bandwidth
2.5 MHz/5 MHz/10 MHz real
5 MHz/10 MHz/20 MHz complex - Output data rate: 30 MSPS to 160 MSPS
- See data sheet for additional features
The AD9262 is a dual, 16-bit analog-to-digital converter (ADC) based on a continuous time sigma-delta (Σ-Δ) architecture that achieves -87 dB of dynamic range over a 10 MHz input bandwidth.
The integrated features and characteristics unique to the continuous time Σ-Δ architecture significantly simplify its use and minimize the need for external components.
The AD9262 has a resistive input impedance that significantly relaxes the requirements of the driver amplifier. In addition, a 32× oversampled fifth-order continuous time loop filter significantly attenuates out of band signals and aliases, reducing the need for external filters at the input.
An external clock input or the integrated integer-N PLL provides the 640 MHz internal clock needed for the oversampled continuous time Σ-Δ modulator. On-chip decimation filters and sample rate converters reduce the modulator data rate from 640 MSPS to a user-defined output data rate between 30 MSPS to 160 MSPS, enabling a more efficient and direct interface.
The AD9262 incorporates an integrated dc correction and quadrature estimation block that corrects for gain and phase mismatch between the two channels. This functional block proves invaluable in complex signal processing applications such as direct conversion receivers.
The digital output data is presented in offset binary, Gray code, or twos complement format. A data clock output (DCO) is provided to ensure proper timing with the receiving logic. The AD9262 has the added feature of interleaving Channel A and Channel B data onto one 16-bit bus, simplifying on-board routing.
The ADC is available in three different bandwidth options of 2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog supply and a 1.8 V to 3.3 V digital supply, consuming 600 mW. The AD9262 is available in a 64-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
- Continuous time Σ-Δ architecture efficiently achieves high dynamic range and wide bandwidth.
- Passive input structure reduces or eliminates the requirements for a driver amplifier.
- An oversampling ratio of 32× and high order loop filter provide excellent alias rejection reducing or eliminating the need for antialiasing filters.
- An integrated decimation filter, sample rate converter, PLL clock multiplier, and voltage reference provide ease of use.
- Integrated dc correction and quadrature error correction.
- Operates from a single 1.8 V analog power supply and 1.8 V to 3.3 V output supply.
APPLICATIONS
- Baseband quadrature receivers: CDMA2000, WCDMA, multicarrier GSM/EDGE, 802.16x, and LTE
- Quadrature sampling instrumentation
- Medical equipment
- Radio detection and ranging (RADAR)
Documentation
Data Sheet 1
User Guide 1
Application Note 10
Technical Articles 2
Video 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9262BCPZ | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9262BCPZ-10 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9262BCPZ-5 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9262BCPZRL7 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9262BCPZRL7-10 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
| AD9262BCPZRL7-5 | 64-Lead LFCSP (9mm x 9mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Jun 9, 2021 - 20_0126 Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea |
||
| AD9262BCPZ | ||
| AD9262BCPZ-10 | ||
| AD9262BCPZ-5 | ||
| AD9262BCPZRL7 | ||
| AD9262BCPZRL7-10 | ||
| AD9262BCPZRL7-5 | ||
This is the most up-to-date revision of the Data Sheet.
Software Resources
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Request a Driver/SoftwareHardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 3 | ||
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 3 | ||
| AD9510 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
| AD9511 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| I/Q Demodulators with Integrated LO 1 | ||
| ADL5382 | RECOMMENDED FOR NEW DESIGNS | 700 MHz TO 2700 MHz Quadrature Demodulator |
| Series Voltage References 1 | ||
| ADR130 | PRODUCTION | Precision Series Sub-Band Gap Voltage Reference |
| Single-Ended to Differential Amplifiers 3 | ||
| ADA4932-2 | RECOMMENDED FOR NEW DESIGNS | Low Power Differential ADC Driver |
| ADA4937-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
| ADA4938-2 | RECOMMENDED FOR NEW DESIGNS | Ultralow Distortion Differential ADC Driver (Dual) |
Tools & Simulations
AD9262 IBIS Model 1
ADIsimRF
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
Open ToolEvaluation Kits
AD9262 Evaluation Board