ADSP-SC57x and ADSP-2157x Product Family

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

The ADSP-SC57x/ADSP-2157x processors are members of the SHARC^® family of products. The ADSP-SC57x processor is based on the SHARC+^® dual-core and the arm^® Cortex^®-A5 core. The ADSP-SC57x/ADSP-2157x SHARC processors are members of the single-instruction, multiple data (SIMD) SHARC family of digital signal processors (DSPs) that feature Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.

By integrating a set of industry leading system peripherals and memory, the arm^® Cortex-A5 and SHARC processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.

CrossCore Embedded Studio is a world-class integrated development environment (IDE) for the Analog Devices Blackfin^®, SHARC^® and Arm^® processor families. Employing the latest generation of our mature code generations tools, this Eclipse^™ based IDE provides seamless, intuitive C/C++ and assembly language editing, code-gen, and debug support.

CrossCore Embedded Studio also offers Blackfin and SHARC developers highly integrated add-in support for drivers, services, and algorithmic software modules. These include driver support for on chip and off chip peripherals, stacks for Ethernet and USB, a popular real time operating system and file system, and more. It provides an easy to use development framework which includes exceptional integrated multicore development and debug support.

FreeRTOS is a free, scalable real-time operating system. This product supports for the Analog Devices ADSP-BF7xx, ADSP-215xx and ADSP-SC5xx (ARM Cortex-A5, ARM Cortex-A55 and SHARC+ cores) processor families.

FreeRTOS is a low memory operating system developed for embedded systems. It supports many common operating system concepts such as timers, events, mutexes, semaphores tasks and semaphores; all of which can be created dynamically or statically. It has a scheduler which can be configured to be preemptive or co-operative, with optional time slicing.

FreeRTOS is royalty free and is provided with non-GPL licensing.

FreeRTOS for Analog Devices Processors is supported by the CrossCore Embedded Studio development environment.

FreeRTOS for Analog Devices Processors is available as source from GitHub, or via an Add-In for CrossCore Embedded Studio which simplifies creation and configuration.

An innovative approach to design has resulted in a TCP/IP stack with an extremely high-speed data transfer rate, with minimal system resource requirements. Tests have shown that packet processing runs up to four times faster than comparable embedded stacks, while using around 14 KB of ROM, in a typical application scenario.­

RAM requirements can vary widely depending on application needs but are typically as low as 12kB. It is possible, with a minimum configuration UDP application, to use less than 5kB of ROM and a few hundred bytes of RAM (plus network buffers).

Please visit Tuxera's HCC Embedded Networking Page for more details and the demonstration projects for ADSP-SC573, ADSP-SC589, ADSP-SC594, and ADSP-SC598 page to find free demonstration projects for the ADSP-SC57x, ADSP-SC58x, and ADSP-SC59x processors

The USB Host stack is scalable. It includes many host class drivers that enable an embedded host to control a variety of USB devices including pen-drives, printers, audio devices, joysticks, virtual serial ports and network interfaces. It supports EHCI, OHCI, and non-standard USB host controllers.

The USB Device stack allows developers to integrate USB device functionality into their embedded devices. It includes many device class drivers that give the device functional possibilities, including operating as a pen-drive, virtual serial port, joystick, audio system or a network card.

HCC Embedded also provides a full software OTG Stack that supports the SRP and HNP protocols to negotiate between two connected devices in order to decide which of them operates as the host.

Please visit Tuxera's HCC Embedded USB Overview page for more details and the demonstration projects for ADSP-SC573, ADSP-SC589, ADSP-SC594, and ADSP-SC598 page to find free demonstration projects for the ADSP-SC57x, ADSP-SC58x, and ADSP-SC59x processors.

HCC Embedded's FAT from Tuxera can interface with any type of sector-based media. Typically, this might be an SD/MMC card, Compact Flash card, or USB pen drive, but it can be any device that is arranged as an array of logical sectors.

Please visit Tuxera's HCC Embedded FAT page for more details and the demonstration projects for ADSP-SC573, ADSP-SC589, ADSP-SC594, and ADSP-SC598 page to find free demonstration projects for the ADSP-SC57x, ADSP-SC58x, and ADSP-SC59x processors.

The Linux Add-In for ADSP-SC5xx provides users with the open, flexible world of Linux coupled with the world-class integrated development environment (IDE) of Analog Devices CrossCore Embedded Studio.

The Linux Add-In for ADSP-SC5xx includes pre-built images that allow users to easily deploy a highly configured Bootloader, Kernel and filesystem on to the ADSP-SC589, ADSP-SC584 and ADSP-SC573 EZ-Kit, providing users with application level access to the peripherals available on the EZ-Kit. Supported drivers include USB, SPORT, I2C, Link Port, SPDIF, CAN, SD Card and Ethernet.  Sources for the Kernel and file system are also provided and are easily re-configurable for user developed hardware.

The ADSP-SC573 processor is a member of the SHARC^® family of products. The ADSP-SC573 processor is based on the SHARC+ dual-core and the arm^® Cortex-A5TM core. The ADSP-SC573 SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices Super Harvard Architecture. These 32-bit/40- bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with their large onchip SRAM, multiple internal buses to eliminate I/O bottlenecks, and innovative digital audio interfaces (DAI). New enhancements to the SHARC+ core add cache enhancements, branch prediction, and other instruction set improvements—all while maintaining instruction set compatibility to previous SHARC products. The EZ-KIT ships with all of the necessary hardware to get you up and running and start the evaluation immediately