ADSP-21362
PRODUCTIONHigh Performance 32-Bit Floating-Point SHARC Processor for Automotive Audio
Part Details
- 333MHz /1.8 GFLOPs SIMD SHARC core supporting IEEE 32-bit floating-point, 40-bit floating-point and 32-bit fixed-point data types
- 25 zero-overhead DMA channels
- Digital Audio Interface (DAI) enabling user-definable access to peripherals including an S/PDIF Tx/Rx, 8-channel asynchronous sample rate converter, and Data Transmission Content Protection hardware accelerator
- 6 serial ports (SPORTs) supporting I2S, left-justified sample pair, and TDM modes
- 2 SPI-compatible ports supporting master and slave modes
- 16 Pulse Width Modulation (PWM) channels
- 3 full-featured timers
- 136-ball MBGA and 144-Ld LQFP E-Pad
package options - Commercial and Industrial temperature ranges
The third generation of SHARC® Processors, which includes the ADSP-21261, ADSP-21262, ADSP-21266, ADSP-21267, ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366, offers increased performance, audio and application-focused peripherals, and memory configurations capable of supporting surround-sound decoder algorithms. All devices are pin-compatible and completely code-compatible with all prior SHARC Processors. These members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.
The ADSP-21362 offers the highest performance – 333 MHz/2 GFLOPs -- within the third generation SHARC Processor family. This level of performance makes the ADSP-21362 particularly well suited to address the increasing requirements of the professional and automotive audio market segments. In addition to its higher core performance, the ADSP-21362 includes additional value-added peripherals such as an S/PDIF transmitter/receiver, 8-channel asynchronous sample rate converter, and a hardware Digital Transmission Content Protection (DTCP) encryption/decryption block.
Third generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Audio Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, DTCP Accelerator, and an 8-Channel asynchronous sample rate converter block.
Documentation
Data Sheet 1
User Guide 4
Application Note 44
Processor Manual 4
Product Highlight 1
Software Manual 11
Emulator Manual 3
Integrated Circuit Anomaly 1
Product Highlight 1
This is the most up-to-date revision of the Data Sheet.
Software Resources
ADSP-2136x Application Code Examples - Single Channel 13
- Single-Channel Block FIR
- Single-Channel Complex Block FIR
- Single-Channel Complex Vector Add
- Single-Channel Complex Vector DOT Product
- Single-Channel Complex Vector Multiply Accumulate
- Single-Channel Complex Vector Multiply
- Single-Channel Complex Vector RAD2 FFT
- Single-Channel Complex Vector RAD4 FFT
- Single-Channel Matrix by Matrix
- Single-Channel Matrix by Vector
- Single-Channel Real Rad2 FFT
- Single-Channel Single Sample FIR
- Single-Channel Vector Maximum
ADSP-2136x Application Code Examples - Multi Channel 8
Software & Tools Anomaly 1
CrossCore® Embedded Studio
CCES is a world-class integrated development environment (IDE) for the ADI Blackfin®, SHARC® and Arm® processor families.
View DetailsSigmaStudio®
Graphical development tool for programming, development, and tuning software for ADI DSP audio processors and A2B® transceivers.
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