AD9550
RECOMMENDED FOR NEW DESIGNSInteger-N Clock Translator for Wireline Communications
- Part Models
- 2
- 1ku List Price
- Starting From $4.18
Part Details
- Converts preset standard input frequencies to standard output frequencies
- Input frequencies from 8 kHz to 200 MHz
- Output frequencies up to 810 MHz LVPECL and LVDS (200 MHz CMOS)
- Preset pin-programmable frequency translation ratios
- Single-ended CMOS reference input
- On-chip VCO
- Two output clocks (independently programmable as LVDS, LVPECL, or CMOS)
- Single supply (3.3 V)
- Very low power: <450 mW (under most conditions)
- Small package size (5 mm × 5 mm)
- Exceeds Telcordia GR-253-CORE jitter generation, transfer and tolerance specifications
The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended input reference signal at the REF input.
The AD9550 is pin programmable, providing a matrix of standard input/output frequency translations from a list of 15 possible input frequencies to a list of 51 possible output frequency pairs (OUT1 and OUT2).
The AD9550 output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9550 is implemented in a strictly CMOS process.
The AD9550 operates over the extended industrial temperature range of −40°C to +85°C.
APPLICATIONS
- Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators
- Flexible frequency translation for wireline applications such as Ethernet, T1/E1, SONET/SDH, GPON, xDSL
- Wireless infrastructure
- Test and measurement (including handheld devices)
Documentation
Data Sheet 1
User Guide 1
Product Selection Guide 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9550BCPZ | 32-Lead LFCSP (5mm x 5mm w/ EP) | ||
| AD9550BCPZ-REEL7 | 32-Lead LFCSP (5mm x 5mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
May 11, 2014 - 13_0231 Assembly Transfer of Select 4x4 and 5x5mm LFCSP Products to STATS ChipPAC China. |
||
| AD9550BCPZ | PRODUCTION | |
| AD9550BCPZ-REEL7 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock Distribution Devices 8 | ||
| ADCLK925 | RECOMMENDED FOR NEW DESIGNS | Ultrafast SiGe ECL Clock/Data Buffers |
| ADCLK944 | RECOMMENDED FOR NEW DESIGNS | 2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer |
| ADCLK948 | RECOMMENDED FOR NEW DESIGNS | Two Selectable Inputs, 8 LVPECL Outputs SiGe Clock Fanout Buffer |
| ADCLK854 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer |
| ADCLK846 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer |
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Clock Generation Devices 1 | ||
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| Positive Linear Regulators (LDO) 2 | ||
| ADP150 | PRODUCTION | Ultralow Noise, 150 mA CMOS Linear Regulator |
| ADP151 | PRODUCTION | Ultralow Noise, 200 mA, CMOS Linear Regulator |
Evaluation Kits
AD9550 Evaluation Board